ghattasak
Member level 1
if i have a array of 0 to M ot std_logic in vhdl and i want to test if it is set having all bits 1, is it advised to use "and gate" or should i use an if statement. what is the difference in hardware?
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
No, "others" can only be used in an assignment.done_sort <= '1' when done_arr =((others => '1')) else '0';
can i write it like this ? supposedly done_arr is an array of 0 to M and i want it to varry depending on M and not set up like a 1000 1's
Code VHDL - [expand] 1 2 3 4 5 constant all_ones : std_logic_vector(0 to M) := (others => '1'); ... done_sort <= '1' when done_arr = all_ones else '0';