aria62
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Hi.
I have created a gate-level netlist from my design using Synopsys DC. Now I am trying to do the scan insertion in the Tessent shell. I assume that after reading the Verilog netlist, Tessent needs to read a library file with the .lib extension. From an example, I noticed that this library is something like Spice library that contains some models of flip-flops and logic gates. Does anybody know how this library can be obtained? Should I create some libraries manually for the scan insertion?
Having said that I have used freepdk45 for creating the gate-level netlist and it doesn't contain any lib file for scan insertion.
Thanks
I have created a gate-level netlist from my design using Synopsys DC. Now I am trying to do the scan insertion in the Tessent shell. I assume that after reading the Verilog netlist, Tessent needs to read a library file with the .lib extension. From an example, I noticed that this library is something like Spice library that contains some models of flip-flops and logic gates. Does anybody know how this library can be obtained? Should I create some libraries manually for the scan insertion?
Having said that I have used freepdk45 for creating the gate-level netlist and it doesn't contain any lib file for scan insertion.
Thanks