diemilio
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I'm designing BGR using a very well known topology (Fig 1). When I look at the current vs. temp behavior through the branches connected to the positive and negative inputs of the correction amp, I get the expected response (red trace in Fig 2), but when I check the mirrored current to the output the temperature performance is severely degraded (blue trace in Fig 2)!!
I'm using ideal resistors with no tempco and the size ratio of the top PMOS is 1:1. The design is being implemented in 0.18 um and I've implemented a very similar topology in 0.5 um and didn't see this happening.
Can someone give me an idea of where this is coming from??
Thanks,
diemilio
I'm using ideal resistors with no tempco and the size ratio of the top PMOS is 1:1. The design is being implemented in 0.18 um and I've implemented a very similar topology in 0.5 um and didn't see this happening.
Can someone give me an idea of where this is coming from??
Thanks,
diemilio