raghavathej
Junior Member level 3
Hi everyone,
I am using Tanner EDA Tools.
I have constructed a simple inverter in L-EDIT, while checking
for DRC Errors, there are hundreds of errors, this is because i draw everything
from scratch (much below transistor level, as we dont have PMOS and NMOS layout
symbols to use directly, i start by building the same from source, drain, gate etc).
I have also used Mentors pyxis layout editor & cadence Virtuoso layout editor. The DRC errors
over there are very easy to fix because i directly use PMOS and NMOS Transistor layouts directly.
My questions are :-
1. Will i get PMOS and NMOS layouts directly in Tanner EDA Tools as Well (I am using v16.0) ? if so please share the procedure...
2. Do i have autoroute option in Tanner EDA like Mentors Pyxis/ Cadence Virtuoso ? if so share the same..
3. Why hasn't Tanner EDA been as popular as Mentor/Synopsis/Cadence Tools considering that Tanner can also generate GDSII file.
Awaiting for you reply, Thanks in advance !!!
I am using Tanner EDA Tools.
I have constructed a simple inverter in L-EDIT, while checking
for DRC Errors, there are hundreds of errors, this is because i draw everything
from scratch (much below transistor level, as we dont have PMOS and NMOS layout
symbols to use directly, i start by building the same from source, drain, gate etc).
I have also used Mentors pyxis layout editor & cadence Virtuoso layout editor. The DRC errors
over there are very easy to fix because i directly use PMOS and NMOS Transistor layouts directly.
My questions are :-
1. Will i get PMOS and NMOS layouts directly in Tanner EDA Tools as Well (I am using v16.0) ? if so please share the procedure...
2. Do i have autoroute option in Tanner EDA like Mentors Pyxis/ Cadence Virtuoso ? if so share the same..
3. Why hasn't Tanner EDA been as popular as Mentor/Synopsis/Cadence Tools considering that Tanner can also generate GDSII file.
Awaiting for you reply, Thanks in advance !!!