T-points in allegro. do we really need them?

[buenos]

t points in allegro

hi

do we really need to use T-ponts and net scheduling in Cadence Allegro PCB?

I mean for example if someone copies a piece of layout (like an sodimm reference design to onboard memory-down), and wants to route signals to its pins, do we always need these T-points? I think we could route/constrain those signals from chip pin to chip pin, instead of chip-pin to copied-design.

are there cases when we can not avoid using these T-points? where we can not constrain pin-to-pin? for example?

 

[majnoon]

allegro t point

It depends on design. Usually if you are not Daisy Chaining then T junction can be used.

M

 

[buenos]

are there cases where it is a designer's choice to use a T-point+netscheduling or do differently.

 

[majnoon]

It depends on design. For example if you have memory lines preference is Daisy Chain not T-Point.
Check device data sheet and see what manufacturer suggest.

M