buenos
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t points in allegro
hi
do we really need to use T-ponts and net scheduling in Cadence Allegro PCB?
I mean for example if someone copies a piece of layout (like an sodimm reference design to onboard memory-down), and wants to route signals to its pins, do we always need these T-points? I think we could route/constrain those signals from chip pin to chip pin, instead of chip-pin to copied-design.
are there cases when we can not avoid using these T-points? where we can not constrain pin-to-pin? for example?
hi
do we really need to use T-ponts and net scheduling in Cadence Allegro PCB?
I mean for example if someone copies a piece of layout (like an sodimm reference design to onboard memory-down), and wants to route signals to its pins, do we always need these T-points? I think we could route/constrain those signals from chip pin to chip pin, instead of chip-pin to copied-design.
are there cases when we can not avoid using these T-points? where we can not constrain pin-to-pin? for example?