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I don't think systemC will die. It is good for system modelling. For those having software development background, systemC is easy to get started. And it is free and source open. This makes it more accessable and amiable, which can attract a large group of users, resulting in a long need of existence and development of systemC.
System C is gaining momentum. It is mainly being used as a replacement of HVLs like Vera and specman. Nowadays companies does not want to spend extra amount on these tools instead prefer to use SystemC which is as a part of the Simulators itself. Cadence has created their own library of systemc functions which are powerful and can be used to create environments euivalrn in Specman and Vera
SystemC was initially launched as System Description Language that reside at the higher level than Verilog/VHDL as Hardware Description Language. However, SystemC need to be translated into Verilog/VHDL for further systhesis process. In high performance hardware design, SystemC is not so suitable to be totally replace Verilog/VHDL. Instead, it is very good for behavior description such as state-machine design. Anyway, SystemVerilog seems to be more comprehensive solution in this senario. With this consideration, SystemC would be transformed into the future platform in testbench design for verification purpose since the hardware complexity become higher and higher. The competition of SystemC and e-language would be raised soon.
there are many pure alogorithm job that need to use C/C++. but there is big gap between C-HW design. System C could be a good tool to explore different architecture, since at this stage, there is no HW building block and the test environment is all C.
here system verilog is useless.
for verification, C could give you all freedom, I like that. and systemC is opensource, pure C++, no license fee, all you need is a compiler like gcc. and I think after some time, there will be a lot of libraries that can be freely used. most simulator are support co-simulation now.
but verilog will exist, I do not think system c synthesis is good idea, and write low level HW is not system c's job.
I think systemC, systemverilog and VerilogHDL will coexist for a long time. SystemC development tools are relatively expensive. If its price goes down, it will account for a larger market.
SystemC will not die for lot of years because of following:
- it is ideal for SW/HW co-design; actuallty there is no other language (if we ignore other C++ library languages) on the market in which you coud do this
- it is ideal for SW/HW partitioning, architectural exploration, platform/system modeling, real bandwidth calculation
- it is free; of course you could buy Simulator with better debugging support but if you are startup and don't have money for expencive licenses it is ideal; there are also free tools for Verilog/VHDL->SystemC translation, so you could reduce usage of HDL simulator on very minimum
- it is also perfect for SW/HW cosimulation, including integration with ISS of various processors (this days all ISS are actually written in SystemC)
- it is great for block-level verification (HDL - SystemC cosimulation)
- if you know what are you doing (have HW and not SW way of thinking), SystemC is perfect for top-down design aprouch: start from un-timed behavioral model and refine it up to the level where you could plug-in HDL module implementation in your SystemC system - no more block-level test environment development
From my point of view, in a few years e will be dead (even it is the best verification language today), Verilog, Vera will be alive only as a sub-set of SystemVerilog, VHDL will be alive primary in Europe (used together with SystemC, where all verification is done in systemC, from block to platform level), SystemVerilog will be used for design and verification up to the some level, but today everybody make SoCs and each SoC has several CPUs, and you could not do SW/HW coverification and codesign in SystemVerilog.
SystemC is far better and more open concept then SystemVerilog (Synopsys evidently realized that when they made their famous turn from SystemC to SystemVerilog - you could not have monopol where things are open).
To be honest, we are used to fancy tool suport which allow us not to think to much.
Using of SystemC will add new live to ASIC comunnity - it will not be important are you rich enough to buy 1000 licenses of fastest simulator on the market ...
My company is using SystemC too. I think it fit system modeling well, but is not fit to synthesis.SystemC is enhanced to fit synthesis ,well SystemVerilog which is superset of verilog for verification.
From the system design point, I think systemc is a powerfull tool to modeling, and for systemc is based on C++, and it can transform c and C++ models very easy. But there are some defects in SystemC:
1. It is simulation time is not fast enough, only 1/3 to RTL.
2. There are few free systemc ip for platform establish.
Hello...We tried to use SystemC for our grad project and after about 5 months we figured out that it was a compplete waste of time. SystemC can be used for modelling purposes and comparing different architecures, but we couldnt find a tool to synthesize our designs on an FPGA ! So, I guess it's currently a modelling rather than a synthesis language. It just needs some time for it's tools to evolve.
Wesam Gobran
Years ago lot of people said systemC would be the perfect replacement of VHDL & verilog and it's gonna to be next generation efficient HDL. However till now, SystemC has not been in the HDL stage even as a minor role.
Synopsys declared that they would abandon SystemC EDA software development.
All attempts on SystemC proved to be an abortion? :?:
SystemC now is IEEE is standard, and there are also companies providing syntheis tools.
It will take time to get popular. First the tools need to get mature, Second it takes time for RTL guy to switch to SystemC. (Hey, it is C++, my old colleague get puzzled that he can not move a module in different order in s/w C code as he would in RTL as the way of port mapping )
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