System Verilog type "logic"

[shaiko]

As far as I understand -
Verilog uses type "reg" for flip flops and type "wire" for combinatorial logic.

System Verilog on the other hand - has type "logic"
Is this type the same as "signal" in VHDL?
Can it be used interchangeably instead of "reg" and "wire" to describe any logic ?

 

[sharath666]

In SV, logic is used for registers as well as wires while wire is used only for multi driven signals as only wires have a resolution function associated with them.
yes...something similar to signal in vhdl.

 

[ads-ee]

reg isn't always used for flip-flops, that is a misconception that many have. The example shown in the link, which I've copied below shows what I mean.
https://stackoverflow.com/questions/13282066/difference-of-systemverilog-data-types-reg-logic-bits

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Code Verilog - [expand]
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wire w_data;
assign w_data = y;
 
// Same function as above using reg
reg r_data;
always @* 
  r_data = y ;
 
// Now using logic...
// same as the wire from above, but using logic type.
logic  w_data;
assign w_data = y;
 
// Same function as reg above, but using logic type
logic r_data;
always @* 
  r_data = y ;

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Personally I think the addition of this new type was pandering to the complaints that new learners were getting so confused over reg meaning "register" (a.k.a Flip-flops). I think this misconception reflects more on new learners not being studious enough or very poor instruction/instruction_materials. I'm not entirely sure I like the idea of a magic type that changes it's behavior depending on how it is used.

 

[TrickyDicky]

As far as I understand -
Verilog uses type "reg" for flip flops and type "wire" for combinatorial logic.

System Verilog on the other hand - has type "logic"
Is this type the same as "signal" in VHDL?
Can it be used interchangeably instead of "reg" and "wire" to describe any logic ?

Reg and wire are just data types. As stated above, a reg is just a data type that can be assigned how you want where you want. It doesnt necessarily make a register. The logic data type was introduced in SV to stop people confusing the two (and theres no reason in SV just to make everything logic, and ignore reg and wire completly).

A signal in VHDL is equivalent to a non-blocking assignment in Verilog.
A variable in VHDL is equivalent to a blocking assignment in verilog

 

[shaiko]

and theres no reason in SV just to make everything logic, and ignore reg and wire completly

I understand that...using "wire" and "reg" increases code readability
but is it legal to use "logic" instead of both ?

 

[ads-ee]

yes, see the link I posted, or the code I pasted from the link. I'm pretty sure it can also be used in an edge triggered always block too. I don't use logic, mainly because of it's "magical" qualities and the fact that not all tools support SV completely.

 

[TrickyDicky]

I understand that...using "wire" and "reg" increases code readability
but is it legal to use "logic" instead of both ?

It only increases readability for people that write correct code.
If you come into it thinking reg type will always make a register, you're bound to stumble.

Yes, you can use logic anywhere you could previously use reg or wire.
Note, there is also the "bit" data type that is a 2 state type.

 

[dave_59]

reg and logic are synonyms for the same data type in SystemVerilog; one that has 4 states. wire is not a data type, it is a kind of signal. You should look at my blog post: https://go.mentor.com/wire-vs-reg