shaiko
Advanced Member level 5
As far as I understand -
Verilog uses type "reg" for flip flops and type "wire" for combinatorial logic.
System Verilog on the other hand - has type "logic"
Is this type the same as "signal" in VHDL?
Can it be used interchangeably instead of "reg" and "wire" to describe any logic ?
Verilog uses type "reg" for flip flops and type "wire" for combinatorial logic.
System Verilog on the other hand - has type "logic"
Is this type the same as "signal" in VHDL?
Can it be used interchangeably instead of "reg" and "wire" to describe any logic ?