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system generator13.1 and matlab2009b

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I'm using Xilinx 13.1 evaluation version.I'm trying to generate a VHDL code for the chain code algorithm written in matlab.
**Error in port widths or dimensions. Output port 1 of 'untitled/Image From Workspace' is a [125x125] matrix
**Error in port widths or dimensions. Input port 1 of 'untitled/Gateway In' is a one dimensional vector with 1 elements
Can anyone please help me to get out of this errors
Thanks in advance
 

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