System C synthesis - a question

[patchquinn]

System C synthesis

Can anyone tell me if a SystemC description is first translated to verilog, when synthesised. I am certain I read this somewhere, in a paper. but a colleague disaggrees with be saying that synthesis is possible from straight from an RTL systme C description.

 

[ramesh]

I don't know about SystemC. But Handel-C used for similar application can be synthesized directly to get EDIF file which is further used for place and route. If one needs verilog or VHDL output, that can also be obtained using Celoxica DK software. So that in the second step the Verilog and VHDL can be synthesized to get EDIF file.

 

[geconom]

The same works with SystemC, at least in the general case. Some researcher may have used Verilog in order to employ a Verilog synthesizer. Tools like Synopsys CoCentric SystemC compiler do not need an intermediate Verilog translation.

 

[patchquinn]

I know the synopsis tool doesn't need a Verilog intermediate stage, but I wonder if it creates one itself. This is what i read in a paper entitled using SystemC for Hardware design, where it says that the synthesis is devided into two steps by the Synopsis Compiler, first the SystemC RTL is translted into Verilog then the verilog is synthesised. (this is interesting, and could be very useful., it also means synthesis errors can be more difficult to trace. )
But I have not found this backed up anywhere else. Nor have I ever used systemC so I don't know. But am interested in knowing as I may use it in the immediate future.
P

 

[geconom]

Can you give the reference for the paper?

 

[patchquinn]

Mario Steinert, Steffen Buch,"Using SystemC for Hardware Design Comparison of results with VHDL, Cossap and CoCentric", CPD AA, Infineon Technologies AG, 2002. This was a paper presented at SNUG Europe 2002 (SNUG: Synopsis User groups)
Would upload a pdf if I had one available, but have only my notes and a few quotes from the paper. Read it months ago.

 

[spacekim]

Using SystemC for Hardware Design....

 

[corgan]

SystemC is a good language for modeling, but I don't think systemC is a good language for design actually.
Current HDL design envrionment is getting
robust for production. How many years
could SystemC to get into inductry without many tools support?

 

[steshenko]

good link
https://www.systemc.org
if you need i can upload
Describing
Synthesizable RTL
in SystemC™
by Synopsys

 

[ramesh]

Re: System C synthesis

use celoxica dk1.1 based on Handel-C.

 

[it_boy]

Re: System C synthesis

I want to know how good celoxica is.
If I code with Handle C and synthesise using celoxica, will it be as good as synthesising an RTL?
Or is it atleast nearby?

Thanx

 

[geconom]

Re: System C synthesis

Here are some examples. Check for yourself

 

[it_boy]

Re: System C synthesis

thanx a lot geconom.
I've never tried the tool so far. I just downloaded an eval vrsion of DK1.1
I'll try.

 

[Ohh2]

Re: System C synthesis

I think if you want to design a System-on-a-Chip, which consists of both hardware and software, then SystemC is a good choice as a modeling language. However, SystemC is based on a refinement design approach. That means, you can model the system at different levels of abstraction (untimed or timed), but the final implementation of the hardware part must be described at the RT level and can be further processed by SystemC HW systhesis tool.

 

[wetdan]

Re: System C synthesis

SystemC is just like Verilog, which has a subset syntax for RTL description. Maybe it is not a very good language for synthesis. But As a system level description language, you can use it all the way from system level modelling(HW/SW co-simulation) to RTL synthesis with a single language, doesnt it sounds great?

 

[star123]

Re: System C synthesis

Here is the document about the Synthesizable RTL subset of SystemC
for C@Centric SystemC Compiler.
. It is a PDF file
. 138 page

 

[apex]

SystemC is the expandition of C to the hardware. It's supportted by the pricesion sythesis tool from Mentor Graphics.

 

[leonardo1]

Re: System C synthesis

do you know where to download an eval version of systemC? Is it supported by modelsim 5.8? thanks

 

[wufengbo]

Yes,SystemC is supported by modelsim v5.8.But it isn't supported on windows platform.

 

[sunroof]

good link
https://www.systemc.org
if you need i can upload
Describing
Synthesizable RTL
in SystemC™
by Synopsys

Please upload it. Thanks,

r u talking about this paper?

**broken link removed**