synthesis using cadence

[guzhal]

cadence synthesis

1.can anyone give me the whole flow of pks_shell cadence tool .I am writing a vhdl file and I can go upto the" build generic" and optimize(giving error: floorplan area not specified)and write it into a verilog netlist file.if i give this verilog netlist file as input to the encounter ,it is giving error in the verilog file.

2.Does encounter tool takes input of netlist in verilog format only or a vhdl netlist can be given to it .....?

:?:
guzhal

 

[gliss]

set_generated_clock

PKS is Physically Knowledgable Synthesis. For that you NEED floorplan information. That means you have to go into a tool like Encounter, write out a DEF file and go back into PKS.

If you have any other issues, post your exact error messages.

 

[vlsi_whiz]

synthesis in cadence

Hi,

Here's the entire flow for synthesis including scan-insertion. I didnt include the PKS flow as I usually do the P&R manually in SoC Encounter. This flow will get you to the output verilog netlist.

SoC Encounter takes in only Verilog netlist and does not read VHDL files/netlists. You can synthesize VHDL files using PKS or Build Gates and write out a verilog netlist for P&R.

Here's the entire flow:

# -------------------------------------------------
# Setup Lib and Dirs
# change lib_dir to point to the synthesis library you use and the directory structure you follow.

set <lib_dir> ..
set tcl_dir $lib_dir/tcl
set rtl_dir $lib_dir/rtl
set lib_dir $lib_dir/lib
set rep_dir $lib_dir/rpt
set adb_dir $lib_dir/adb

# ------------------------------------------------

# ------------------------------------------------
# Set Globals

set_global message_verbosity_level 8
set_global echo_commands true
set_global report_precision 5
set_global fix_multiport_nets true 
set_global sdc_write_unambiguous_names false
set_global line_length 1000
# -----------------------------------------------

# -----------------------------------------------
# Read Tech Libs

read_tlf $lib_dir/slow_4.3.tlf
read_tlf $lib_dir/pllclk_slow_4.3.tlf
read_tlf $lib_dir/ram_128x16A_slow_4.3.tlf
read_tlf $lib_dir/ram_256x16A_slow_4.3.tlf
read_tlf $lib_dir/rom_512x16A_slow_4.3.tlf
read_library_update $lib_dir/tpz973gwc-lite_4.3.tlf

set_global target_technology slow

# Report the library
report_library
# -----------------------------------------------

# -----------------------------------------------
# Read source files (VHDL or Verilog)

read_verilog <path to file/filename.v>

or

read_vhdl <path to file/filename.vhd>

# Build the generic gate level netlist
do_build_generic

# Check the netlist for errors/warnings
check_netlist -verbose
# -----------------------------------------------

# -----------------------------------------------
# Set the scan assertions
issue_message -type info "Mapping test_control module"

set_current_module test_control
do_xform_map
set_dont_modify [find -hier -module test_control]
set_current_module [find -module dtmf_chip]

issue_message -type info "Setting up for scan synthesis in chain mode"

set_scan_style muxscan
set_global dft_scan_path_connect tieback
set_global dft_scan_avoid_control_buffering true
set_scan_mode IOPADS_INST/Pscanenip/C 1

check_dft_rules

# Fix errors in DFT structure
set_test_mode_setup test_mode 1
set_test_mode_setup reset 0
check_dft_rules
# ------------------------------------------------

# ------------------------------------------------
# Set the timing and synthesis constraints
# ----------------------------------------

# Setting up Hierarchical and Timing Context"
issue_message -type info "--> Setting up Hierarchical and Timing Context ..."

set_current_module dtmf_chip
set_top_timing_module dtmf_chip

# Setting Ideal Clocks" 
issue_message -type info "--> Setting Ideal Clocks ..."
set_clock vclk1 -period 6.0 -waveform { 0 3.0 }
set_clock vclk2 -period 12.0 -waveform { 0 6.0 }

# Setting Primary Clocks
issue_message -type info "--> Setting Primary Clocks ..."
set_clock_root -clock vclk1 [find -port refclk ]

# Setting Internally Generated Clocks 
issue_message -type info "--> Setting Internal Clocks ..."

set_generated_clock -name vclk1_int1 -from DTMF_INST/TDSP_CORE_INST/DATA_BUS_MACH_INST/clk  

-divide_by 2 DTMF_INST/TDSP_CORE_INST/DATA_BUS_MACH_INST/write_reg/Q 
set_generated_clock -name vclk1_int2 -from DTMF_INST/DMA_INST/clk  -divide_by 2  

DTMF_INST/DMA_INST/write_reg/Q

issue_message -type info "--> Setting Muxed Clocks ..."
set clock_pin [find -hier -pin DTMF_INST/TEST_CONTROL_INST/m_clk]
set drive_pin [get_drive_pin -hier [get_info $clock_pin net] ]
set_clock_info_change -clock vclk1 -pos $drive_pin
set_clock_insertion_delay -pin $drive_pin 2.0

foreach clock {m_rcc_clk m_spi_clk m_dsram_clk m_ram_clk m_digit_clk} {
  set clock_pin [find -hier -pin DTMF_INST/TEST_CONTROL_INST/$clock]
  set drive_pin [get_drive_pin -hier [get_info $clock_pin net] ]
  set_clock_info_change  -clock vclk2 -pos $drive_pin
set_clock_insertion_delay -pin $drive_pin 2.0
}

set_clock_uncertainty 0.25

#Setting Input/Output ports constraints"
issue_message -type info "--> Setting Input/Output ports constraints..."
set_input_delay -clock vclk1 0.5 [ get_names [ find -inputs -no_clocks] ]
set_external_delay -clock vclk1 0.5 [ get_names [ find -outputs port*] ] 
set_external_delay -clock vclk1 0.5 [ get_names [ find -outputs tdigit*] ] 

#Setting Multicycle and False Paths
issue_message -type info "--> Setting Multicycle and False Paths ..."
set_cycle_addition -to DTMF_INST/TDSP_CORE_INST/EXECUTE_INST/acc_reg* 1
set_cycle_addition -to DTMF_INST/TDSP_CORE_INST/EXECUTE_INST/p_reg* 1
set_cycle_addition -to DTMF_INST/TDSP_CORE_INST/EXECUTE_INST/ov_flag_reg* 1

set_false_path -from reset  

set_constant_for_timing 0 test_mode
set_constant_for_timing 0 scan_en

#Setting Design Rules
issue_message -type info "--> Setting Desgin Rules ..."
set_slew_time_limit 2.3 [ find -ports -noclocks * ] 
set_global fanout_load_limit 15

set_drive_cell -cell PDO04CDG  [find -input -noclocks * ]
set_port_capacitance [expr [get_cell_pin_load -cell PDIDGZ -pin PAD]*2.0] [find -output * ]

#Setting wire load models
issue_message -type info "--> Setting wire load..."
set_wire_load TSMC18_Conservative
set_wire_load_mode enclosed
set_wire_load_selection_table WireAreaCon
# --------------------------------------------

# Check the constraints
check_timing -detail

# Creating group paths
set_path_group -name IN  -from [ find -input -noclocks * ]
set_path_group_options IN -target_slack 0.2 -all_end_points

set_path_group -name OUT -to [ find -output * ]
set_path_group_options OUT -target_slack 0.5 -all_end_points

set_path_group -name vclk2_group -clock_from vclk2
set_path_group_options vclk2_group -target_slack 0.0 -all_end_points

set_path_group -name vclk1_group -clock_from vclk1
set_path_group_options vclk1_group -target_slack -1.0 -all_end_points

# Optimize
do_optimize

# Report analysis coverage
report_analysis_coverage > $rep_dir/report_analysis_coverage.rpt
report_analysis_coverage -check_type setup -sort slack > $rep_dir/setup.rpt

# Create timing and area reports
report_timing > $rep_dir/setup_timing.rpt
report_area > $rep_dir/area.rpt

# Write the optimized netlist and database
write_verilog -hierarchical $adb_dir/dtmf_chip_opt.vs
write_adb $adb_dir/dtmf_chip_opt.adb

# Connect the scan chain.  Previously, the scan in has been tied
# to the scan out on each flop.  This will hook scan in to scan out
# of a previous flop.  The tcl script includes the transform
set_number_of_scan_chains 3

set_scan_data {IOPADS_INST/Ptdspip00/C} {IOPADS_INST/Ptdspop00/I} -shared_out
set_scan_data {IOPADS_INST/Ptdspip01/C} {IOPADS_INST/Ptdspop01/I} -shared_out
set_scan_data {IOPADS_INST/Ptdspip02/C} {IOPADS_INST/Ptdspop02/I} -shared_out

set_dft_compatible_clock_domain -sameclock
set_global dft_scan_path_connect chain

do_xform_connect_scan

#check the timing after scan insertion
report_timing -late > $rep_dir/setup_scan_timing.rpt

# incremental timing optimization
set_path_group_options vclk1_group -target_slack 0.0 -all_end_points
do_optimize -incremental -dont_reclaim_area

# Create new timing and area reports
report_timing -late -nworst  5 > $rep_dir/setup_scan_incr_opt_timing.rpt
report_timing -early >  $rep_dir/hold_timing.rpt

# Write the new netlist and database
write_verilog -hierarchical $adb_dir/dtmf_chip.scan.vs
write_adb $adb_dir/dtmf_chip.scan.adb

# Write constraints into Synopsys constraints format (SDC)
write_sdc sdc_out.tcl

# Read constraints in Synopsys constraints format
read_dc_script -ambit bg_constraints.tcl -write_only sdc_out.tcl

# Quit
exit

 

[azerm]

sdc_write_unambiguous_names

Is this flow ok with BG?

 

[diag]

cadence verilog synthesis

i think so .

 

[omara007]

cadence def file

Is this flow ok with BG?

You need to know that BG is almost obsolute now.

 

[aravind]

synthesize design using cadence

why cant you use cadence RTLCompiler synthesis tool. that is much better than pks and bg.