rafimiet
Member level 5
I have a segment of vhdl code as follows:
When I synthesis the code, I get the following error at line 42:
[Synth 8-27] complex assignment not supported
How to rectify this?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 if option = '0' then addr1_1 := 4*addr1_2; ---4xAddress if s_count2 = 0 then block_array(block_index) <= addr1_1; block_index := block_index + 1; s_count2 <= 1; elsif s_count2 = 1 then block_array(block_index) <= addr1_1 + 1; block_index := block_index + 1; s_count2 <= 2; elsif s_count2 = 2 then block_array(block_index) <= addr1_1 + 2; block_index := block_index + 1; s_count2 <= 3; else block_array(block_index) <= addr1_1 + 3; block_index := block_index + 1; option <= '1'; s_count2 <= 0; block_addr <= 0; end if; else addr1_1 := 4*block_array(block_addr); if addr1_1 <= b1'high then if s_count2 = 0 then block_array(block_index) <= addr1_1; block_index := block_index + 1; db_a1 := block_addr;db_a2 := block_addr + 1; s_count2 <= 1; elsif s_count2 = 1 then block_array(block_index) <= addr1_1 + 1; block_index := block_index + 1; s_count2 <= 2; elsif s_count2 = 2 then block_array(block_index) <= addr1_1 + 2; block_index := block_index + 1; s_count2 <= 3; else block_array(block_index) <= addr1_1 + 3; block_index := block_index + 1; if b(block_array(block_addr)) = '1' then block_array(block_addr TO 339) <= block_array(block_addr+1 TO 340); block_index := block_index - 1; else block_addr <= block_addr + 1; end if; s_count2 <= 0; end if; end if; end if;
When I synthesis the code, I get the following error at line 42:
[Synth 8-27] complex assignment not supported
How to rectify this?