[SOLVED] Syntethizable counter

[madalin1990]

I have wrote a code for a stopwatch in verilog.The problem is my Synthesize failed because my counter is not syntethizable.How can I modify it to make it work.Here is the code:
module cnt_0to9(
clk,
en,
rst,
co,
q
);

input clk;
input en;
input rst;
output co;
output [3:0] q;

wire clk;
wire en;
wire rst;
reg co;
reg [3:0] q;



always @(posedge clk,posedge rst)
begin:COUNTER
if(rst == 1'b1)
q <= 4'b0;
else if(en == 1'b1)
q<=q+1;


if(q==4'b1001) begin
q<=4'b0;
co<=1'b1;
end
else begin q<=q+1;
co<=1'b0;

end
end



endmodule

 

[permute]

just use begin/end. the issue is that the counter technically would need to increment on either the clock or the reset. eg "if rst == 1" will be true, which will schedule q <= 0. however, the next statement "if q == 9" might be false. in that case q would instead be scheduled to get q+1. You probably wanted a "begin/end" block for the en == 1 case.

It's not a good idea to use if/else without the begin/end. I've taken to just using "if x begin" "end else if y begin" "end else begin" "end" for the lines. It ends up looking a bit like VHDL actually. but it results in safe code and gets rid of the triple-line "elsif".

 

[madalin1990]

just use begin/end. the issue is that the counter technically would need to increment on either the clock or the reset. eg "if rst == 1" will be true, which will schedule q <= 0. however, the next statement "if q == 9" might be false. in that case q would instead be scheduled to get q+1. You probably wanted a "begin/end" block for the en == 1 case.

It's not a good idea to use if/else without the begin/end. I've taken to just using "if x begin" "end else if y begin" "end else begin" "end" for the lines. It ends up looking a bit like VHDL actually. but it results in safe code and gets rid of the triple-line "elsif".

I have modified the code as you said but still when i'm using xilinx ise webpack to syntesize it gives me this errors:
ERROR:Xst:899 - "../../module pentru fpga/down level/cnt_0to9_noenable.v" line 35: The logic for <q> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "../../module pentru fpga/down level/cnt_0to9_noenable.v" line 29: The logic for <co> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

Here it is the modified code:

//numarator 0->9 reset asincron
module cnt_0to9(
clk,
en,
rst,
co,
q
);

input clk;
input en;
input rst;
output co;
output [3:0] q;

wire clk;
wire en;
wire rst;
reg co;
reg [3:0] q;

always @(posedge clk,posedge rst)
begin:COUNTER
if(rst == 1'b1)begin
q <= 4'b0;
end else
if(en == 1'b1)begin
q<= q+1;
if(q==4'b1001)begin
co <=1'b1;
q<=4'b0;
end else begin

co<=1'b0;
end
end else begin q<=q; end




end
endmodule

---------- Post added at 09:47 ---------- Previous post was at 09:39 ----------

it worked.i had to change to q<=q+1; line to the if(q==1'b1) else.It was logical but i couldn't see it.Thank you permut for guiding me to the answer!!