madalin1990
Full Member level 2
I have wrote a code for a stopwatch in verilog.The problem is my Synthesize failed because my counter is not syntethizable.How can I modify it to make it work.Here is the code:
module cnt_0to9(
clk,
en,
rst,
co,
q
);
input clk;
input en;
input rst;
output co;
output [3:0] q;
wire clk;
wire en;
wire rst;
reg co;
reg [3:0] q;
always @(posedge clk,posedge rst)
begin:COUNTER
if(rst == 1'b1)
q <= 4'b0;
else if(en == 1'b1)
q<=q+1;
if(q==4'b1001) begin
q<=4'b0;
co<=1'b1;
end
else begin q<=q+1;
co<=1'b0;
end
end
endmodule
module cnt_0to9(
clk,
en,
rst,
co,
q
);
input clk;
input en;
input rst;
output co;
output [3:0] q;
wire clk;
wire en;
wire rst;
reg co;
reg [3:0] q;
always @(posedge clk,posedge rst)
begin:COUNTER
if(rst == 1'b1)
q <= 4'b0;
else if(en == 1'b1)
q<=q+1;
if(q==4'b1001) begin
q<=4'b0;
co<=1'b1;
end
else begin q<=q+1;
co<=1'b0;
end
end
endmodule