syntax error, unexpected wire, expecting";"

[macgradywk]

Here is my testbench with syntax error, unexpected wire, expecting";" in line 2, what's wrong?



code:
module test_project1
wire clk,reset;
reg [7:0] port1;
wire [8:0] port2;
reg eof;
integer project1;
initial
project1=$fopen("proj.dat","rb");
always@(posedge clk)
begin
eof=feof(project1);
if(eof==0)
$fscanf(project,"%b",port1);
else
begin
$fclose(project1);
$finish;
end
end
init my_init(clk,reset);
project1 my_project1(port2,port1,clk,reset);
endmodule

 

[dftrtl]

Module without ports has to be end with semicolon like below line
module test_project1;