[SOLVED] Error (10500): VHDL syntax error at lab1.vhd(27) near text "process"; expecting "if"

[shahrilmajid]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity lab1 is
port (in_A, in_B : in std_logic_vector (7 downto 0);
     opcode : in std_logic_vector (1 downto 0);
     out_y : out std_logic_vector (7 downto 0);
     carry : out std_logic);
    end lab1;
    
architecture beh of lab1 is signal tmp    :   
    std_logic_vector(8 downto 0);
    begin
        process    (opcode)
            begin
                     if    opcode = "00" then --cond1
                            tmp <=("0" & in_A) + ("0" & in_B);
                         else if    opcode = "01" then --cond2
                            tmp <=("0" & in_A) - ("0" & in_B);
                          else if    opcode = "10" then --cond2
                            tmp <=("0" & in_A) and ("0" & in_B);
                         else
                            tmp <=("0" & in_A) or ("0" & in_B);
                     end if;
            end process;
out_y <= tmp (7 downto 0);
carry <= tmp (8);
end beh;

could anyone help me.. i am stuck when this error message

 

[barry]

This is your problem:

architecture beh of lab1 is signal tmp    :
    std_logic_vector(8 downto 0);

looks like you pasted something right in the middle of your architecture declaration.

 

[shahrilmajid]

i sss error still remain the same.

 

[barry]

First of all, "signal tmp..." should be on a separate line. It makes no sense the way you have it formatted.

But your main problem is you are using "else if" when I think you mean "elsif". The way you're writing it, every "else if" is creating another level "if" statement.

The error message is telling you that: it's looking for "end if", you're telling it "end process".

 

[dpaul]

@shahrilmajid
For such kind of errors you have the compiler telling you at what line of your code the error is happening.
Why do you not have more patience and review your code with more concentration?
These are really really insignificant errors and just needs careful review.

 

[shahrilmajid]

First of all, "signal tmp..." should be on a separate line. It makes no sense the way you have it formatted.

But your main problem is you are using "else if" when I think you mean "elsif". The way you're writing it, every "else if" is creating another level "if" statement.

The error message is telling you that: it's looking for "end if", you're telling it "end process".

finally it work.. i make it "signal tmp" into a separate line, and change in elsif statement