SYnchronus or Asynchronus reset design in FPGA device ?

[tnguyens]

no resets in fpga

In FPGA design, there is no DFT/Scan insertion so I am thinking to use the synchronous reset for all FF's. Have anyone seen any problems on this synchronus reset design in the FPGA devices ?

Thanks

 

[asic_bh]

fpga unexpected reset

in synchronous reset valid clock has to applied before u apply reset.

 

[vcnvcc]

fpga reset async sync

I think you should use sync. reset. Because your fpga design is working on say x mhz, n async. reset can come at any time, n violates the timing.

Due to sync. reset there wont be any timing violation...

 

[funster]

fpga async or sync reset

using synchronous in FPGA is a good method,

we always do it in our project.

best regards

In FPGA design, there is no DFT/Scan insertion so I am thinking to use the synchronous reset for all FF's. Have anyone seen any problems on this synchronus reset design in the FPGA devices ?

Thanks

 

[echo47]

Async reset is tricky to implement reliably, and sync reset consumes resources, so I almost never use external reset in my projects. The FPGA automatically initializes all flops during configuration. I design my logic modules so in case of some unexpected run-time upset, the logic naturally falls back into normal operation (instead of getting stuck in an invalid state).

 

[sawaak]

Async reset is tricky to implement reliably, and sync reset consumes resources, so I almost never use external reset in my projects. The FPGA automatically initializes all flops during configuration. I design my logic modules so in case of some unexpected run-time upset, the logic naturally falls back into normal operation (instead of getting stuck in an invalid state).

Hi,
can u elaborate this with an example plz.


thanks
sawaak

 

[jjww110]

i always use asyn reset in my project!!

 

[s0shinde]

The best thing is to use reset with async asertion and sync removal.

 

[bansalr]

Yes i agree that in FPGA there is no need of reset. since all the logic cells will be initilized with defined state.

Sync and async have it's own merits and demerits.

but async resets have assertion async and deassertion sync as mentioned in previous post

 

[sheik_vb]

I always use Async. reset in FPGA.

 

[Thinkie]

Use Async reset, but the reset signal to be synchronously generated.


This is quite different from a syncrhonous reset

 

[vcnvcc]

hello bansalr,
can u through some light on "Asynch reset assertion asynch but deassertion sync?????

 

[leongch]

Use Async reset, but the reset signal to be synchronously generated.


This is quite different from a syncrhonous reset

I think what u mean is Async reset in each module, but these async reset signal is generated by a main clock manager which practices syncronous reset.

What is the pro and cons of this kind of implementation in ASIC point of view ?

 

[bansalr]

actually the deassertion of async reset should be synchronized w.r.t to clk and used to avoid violation of reset removal time.

 

[s0shinde]

example code:

always @(posedge Clk or negedge Resetn)
begin
if(!Resetn)
begin
rstn <= 1'b0;
async_rstn <= 1'b0;
end
else
begin
rstn <= 1'b1;
async_rstn <= rstn;
end
end

Use this aync_rstn to reset the flops. For example:

always @(posedge Clk or negedge async_rstn)
begin
if(!async_rstn)
q <= 1'b0;
else
q <= d;
end

 

[hoangthanhtung]

example code:

always @(posedge Clk or negedge Resetn)
begin
if(!Resetn)
begin
rstn <= 1'b0;
async_rstn <= 1'b0;
end
else
begin
rstn <= 1'b1;
async_rstn <= rstn;
end
end

Use this aync_rstn to reset the flops. For example:

always @(posedge Clk or negedge async_rstn)
begin
if(!async_rstn)
q <= 1'b0;
else
q <= d;
end

it is similar to gate_clocking if you want to use synschronous reset.

 

[vcnvcc]

my method of asserting reset Asynchronously and deasserting reset synchronously is this

register that reset signal which comes from outside....now u OR that registered signal with input rest....correct me if im wrong..

 

[s0shinde]

Hello vccvnc,
The functionality you suggested is the same as mine.

Added after 8 minutes:

Hello vccvcn,
The only problem with your circuit is that, if the delays to the 2 inputs of the OR gate are different, there will be some glitches produced, as against the circuit in which I had mentioned. If there are glitches in the aynchronous input itself, they will be present at the output of both our circuits. Nothing against your circuit, just wanted to point it out to you.

Thanks
s0shinde

 

[vcnvcc]

oh Thanks Mr.Shinde