Kaskode
Newbie level 4
Hello all!, I am learning VHDL, sorry if this is too obvious or doesn't make sense at all.
I am trying to implement a FSM whose inputs are only registered synchronously, that is, the output logic process only contains CurrentState in the sensitivity list and it is updated on the rising edge of the clock.
The synthesizer (Quartus II) complains about the inputs not being declared in the sensitivity list, but I want it this way so they are only registered when CurrentState changes.
What am I missing?
I am trying to implement a FSM whose inputs are only registered synchronously, that is, the output logic process only contains CurrentState in the sensitivity list and it is updated on the rising edge of the clock.
The synthesizer (Quartus II) complains about the inputs not being declared in the sensitivity list, but I want it this way so they are only registered when CurrentState changes.
What am I missing?