Sync Reset or Async Reset

[xv_ning999]

Someone has told me that sync reset would meet dft problems.But I cann't understand why.Can anyone here explain to me?

 

[silencer3]

i think sync reset will give more problems for DFT as the reset needs to be bypassed when SCAN testing done done using Scan Enable pin. This requires un-necessary effort and time and logiuc also. But in pure asynchrnous reset (async assertion and sync de-assertion), this problem for DFT wont come into picture.

 

[visualart]

asynchronous reset is better for high performance and the test_bench design.

 

[tarkyss]

i think asyn reset is better too

 

[eda_ak]

This has almost become a religious issue.

You will find followers on both sides. And I am in the async reset camp.

Here is why: If its is aync then the signal can be for a very short duration. If it is a Sync reset then the reset has to be maintained for a very long time. Sync reset has an advantage where the glitch problem is automatically resolved but in the async reset we have to have synchronizing circuit. Also sync reset means tons of extra logic as it becomes part of data path.

... still learning

 

[barkha]

Good paper for Asynchronous & Synchronous Reset Design Techniques
Link : www.sunburst-design.com/papers/ CummingsSNUG2003Boston_Resets.pdf

 

[funster]

I think the best way is synchronize async reset firstly,

then use synchronized signal for internal reset.


best regards

In SoC design, which one is better, Sync Reset or Async Reset?

 

[dr_dft]

Regarding the DFT issue, I think some of the previous posts are misleading. The main goal is make sure that the reset signal does not conflict with our scan operation.

The first thing you need to study is your scan flip-flop library cell to see if scan-enable or reset has higher priority. In general, async reset has the highest priority, so if you use async reset flip-flops, you have to make sure that the reset line connected to this flip-flop is directly controllable from the chip pins during scan.
Flip-flops with synchronous reset may have different flavors. If scan has priority, then there is no issue of reset conflict. However, if reset has priority, then same rules as async reset applies.

The next thing to consider is the whole reset distribution in the chip. If you are using async reset assertion and sync reset deassertion, you must have reset synchronizers in your path, which under scan mode, you must bypass with a scan mode signal.
Same thing with any reset signal staging with flip-flops, synchronous or otherwise. They all need to be bypassed during scan.

 

[soccer]

asynchronous reset better

 

[carrot]

hi

Using synchronous reset leads to infering of extra hardware.
So it is better to use asynchronous reset

 

[gliss]

Async reset

 

[zlychn]

asyn, use reset synchronizer to avoid metastability

 

[zlychn]

The paper Synchronous Resets or Asynchronous Resets describes the sync reset and async reset in detail,includes their difference. It also provides means to solve metastable problem.

 

[rakeshnunna]

Hi Async Reset unlike Sync Reset doesnt have any extra logic between the registers.Hence the data path is clean compared to Sync Reset and results in good performance.But we have to be very careful while using Async reset bcoz there is a risk of violations.