mordak
Member level 5
Hello all,
I have a basic question, when we design a sample and hold or switch cap circuit, the output of the circuit (voltage on the sampling cap in SH, or on the integrating cap in integrator) would not be exactly like the input voltage. Now I am not quite sure about these issues:
1) which parameter defines how much error we can tolerate? I mean if we design a SH with 10 bit resolution, whether its error should be less than Vref/2^N?
2) Difference between the input and output will affect SNR or SNDR? is it a linear phenomena?
3) Say we use it in an ADC, can we treat this error like gain error and offset and if we can disregard it, to what extent?
Any help would be appreciated!
I have a basic question, when we design a sample and hold or switch cap circuit, the output of the circuit (voltage on the sampling cap in SH, or on the integrating cap in integrator) would not be exactly like the input voltage. Now I am not quite sure about these issues:
1) which parameter defines how much error we can tolerate? I mean if we design a SH with 10 bit resolution, whether its error should be less than Vref/2^N?
2) Difference between the input and output will affect SNR or SNDR? is it a linear phenomena?
3) Say we use it in an ADC, can we treat this error like gain error and offset and if we can disregard it, to what extent?
Any help would be appreciated!