Surrounding poly IC caps with substrate contact

[Junus2012]

Hello

I see some designs where people surrounds the CAPs (like poly cap) with substrate contact to the ground, while some designs simply doesnt have it.
What is the advantages of having this contact

Thank you
Regards

 

[dick_freebird]

Cap bottom plate will push / pull on the
substrate through the parasitic capacitance.
The bottom plate is usually the driven plate
in order to preserve signal amplitude and
(non)distortion against that parasitic cap
(a series capacitance of field ox and any
depletion / accumulation MOS "channel"
swing).

Displacement current pushed into the
substrate can produce transients in the
local body potential and this is a stray
signal path, with body effect having about
0.6-0.7X the "weight" of direct Vgs applied
signal.

Many cheapo designs use low cost bulk P-
substrates, and have a high local substrate
access resistance. Epi material (P- on P+)
improves this a lot but the P+ layer still
needs "taps" to drive the local resistance
for any given FET to a consistent low maximum
value.

Around capacitors specifically, a P+ ring (or
even putting cap over NWell, with a hard N+
tie there and then a P+ ring outside that)
are the best you can do at "giving the
displacement current someplace else to go"
- and one that was your choice. Cleaning
up substrate noise sources is always good
hygiene.

 

[Junus2012]

Around capacitors specifically, a P+ ring (or
even putting cap over NWell, with a hard N+
tie there and then a P+ ring outside that)
are the best you can do at "giving the
displacement current someplace else to go"
- and one that was your choice. Cleaning
up substrate noise sources is always good
hygiene.

Dear freebird

Thank you very much for your reply, I will follow your explanation and surround the poly cap with P+ ring contact

 

[Junus2012]

I forgot to ask please,

which is better, to put the cap on NWELL and then use N+ guard ring or keeping it on the P substrate (I am using P wafer) then I use the P+ guard ring

 

[dick_freebird]

NWell will afford additional isolation (from
the substrate). The NWell perturbation can
be held down by good NWell access
resistance / inductance leaving only the
"residue" C-R perturbation to capacitively
couple across the NWell-PSub junction C
and bother the substrate and local devices.

However it would add some incremental area
(the out-nesting of P+ GR around NWell and
its N+ GR) and you might make a value
decision (or, try a couple of design variations
to see whether it helps; substrate coupling
simulation remains something of a mystical
art, or an endless TCAD chore, take your pick).