loic88
Newbie level 2
Hello all,
Being more specialised in ASIC design, I decided today to take a look at FPGA design, and I am super confused by a question I have seen:
In my head, a 6 inputs lookup table is "by definition" a 64 -> 1 MUX, as for each combination of input bits you can define an output. (the 6 bits are then selection bits)....
How would you answer this?
Being more specialised in ASIC design, I decided today to take a look at FPGA design, and I am super confused by a question I have seen:
"What will be the maximum size of a multiplexer if I have a 6 inputs lookup table?"
In my head, a 6 inputs lookup table is "by definition" a 64 -> 1 MUX, as for each combination of input bits you can define an output. (the 6 bits are then selection bits)....
How would you answer this?