Manjularamkumar
Member level 1
Hi ,
I am designing transformer. I follow the substrate definition of inductor on silicon
Top
-------- Strip -cond2
layer3 Via |resi|
-------- Strip cond
Layer2
---------
Layer1
//////GND//////
For transformer design , I have to use two different metal lines
Top
-------- Strip -cond2 cond
layer2 Via |resi| |hole|
-------- Strip diel2 diel
Layer1
//////GND/////
Is it correct sir? T I hereby attached the example design. Please see and tell your suggestion for transformer design.Please help me .
Urgent
I am designing transformer. I follow the substrate definition of inductor on silicon
Top
-------- Strip -cond2
layer3 Via |resi|
-------- Strip cond
Layer2
---------
Layer1
//////GND//////
For transformer design , I have to use two different metal lines
Top
-------- Strip -cond2 cond
layer2 Via |resi| |hole|
-------- Strip diel2 diel
Layer1
//////GND/////
Is it correct sir? T I hereby attached the example design. Please see and tell your suggestion for transformer design.Please help me .
Urgent