Substrate contacts in FDSOI process

[big_fudge98]

Hi all. I am currently designing a chip that is to be operated in mm-wave frequencies. Usually, in mm-wave layouts, we keep as many substrate contacts as possible (to tap the substrate to the ground).
However, in this design, I am using an FDSOI process. In this process, I am unable to find a pcell for substrate contacts. So I was wondering, are substrate contacts not used in FDSOI processes? Why, why not?

Thanks.

 

[Dominik Przyborowski]

In FDSOI devices has 5 or 6 legs always, is means you have contacts for body, wells and general substrate. However, if body, wells and substrate are connected to the same potential only substrate contact are needed.

Some FDSOI processes offers RF an mmw pcell libraries as well.

I am aware of one process which has not substrate contacts, as buried oxide separates whole substrate from all devices. However, I don't believe this process is suitable for mm-wave applications.

So, the question for you, what process you are using and where did you looking for various taps?

 

[big_fudge98]

In FDSOI devices has 5 or 6 legs always, is means you have contacts for body, wells and general substrate. However, if body, wells and substrate are connected to the same potential only substrate contact are needed.

Some FDSOI processes offers RF an mmw pcell libraries as well.

I am aware of one process which has not substrate contacts, as buried oxide separates whole substrate from all devices. However, I don't believe this process is suitable for mm-wave applications.

So, the question for you, what process you are using and where did you looking for various taps?

Hi Dominik,

Thanks for your answer. I am using 22 nm FDSOI from GF.
Like you said, I have access to a mmwave library. The transistros in this are 5 or 6 terminal devices with G,S,D, body, well and substrate terminals. Based on my understanding, a buried oxide layer separates the whole substrate from devices, but the bulk can be accessed if you draw a special layer.

Basically , my original question was this:
- The transistor p-cell has inbuilt substrate contacts. Hence they are isolated well and is not a concern for me at the moment. I have read in textbooks that substrate contacts needed to be placed around capacitors. I was trying to do this. In other GF processes, I have seen a component called 'subc'. I could not find such a component in this PDK. Is this because the capacitor is already isolated from the substrate through the buried oxide?

Your previous answer reminded me of another question that I had.
- Why do mm-wave transistors have additional well terminals? Is it for improved isolation from the surrounding? I guess the nwell needs to be connected to positive supply rail and pwell to negative supply rail (so that the parasitic diodes among them are reverse biased). Is this correct?
- What would happen if I leave these well terminals floating? At schematic level, I can hardly observe any effect, but would there be issues in actual chip?

Thank you.

 

[Dominik Przyborowski]

If you look deeply on PDK documentation you will find devices cross sections. They have BOX only below transistor channel and S/D areas.
The BB process library contains basically three kinds of pcell for each transistor (*fet, *fet_b and *fettw or fetnp), two for resistors and varactors, and one for momcaps.
The FETs pcells *fet are 3 terminal, with back-gate tied to VSS!, *fet_b are 4 terminals (with back-gate), *fetnp are 5 terminals - with additional connection for n-well and *tw with n-well and triple-well (internal p-well) if designer is planning to connect back-gate somewhere else than ground. Basically, 5/6T pcells are wrapper cells containing *fet_b with well diodes.

All pcells has the same layout, which provides swithces to automagically draw guard rings connected to back-gate, nwell and triple well.
You can create contacts manually as well, by choosing fluid guard ring and one of three available templates (for substrate, nwell and triple-well).

I have read in textbooks that substrate contacts needed to be placed around capacitors. I was trying to do this. In other GF processes, I have seen a component called 'subc'. I could not find such a component in this PDK. Is this because the capacitor is already isolated from the substrate through the buried oxide?

This other process was originally IBM CMRF and they have this subc pcell concept (very annoying, so I have even heard about t-shirts with this).
Here, momcaps has additional filling (RX/PC) which can be place below structure (there is a switch in property card) and guardring can be created as above. If you are asking about varactors, they are similar to mosfets and you will need to take care on proper wells connections as well.

- Why do mm-wave transistors have additional well terminals? Is it for improved isolation from the surrounding? I guess the nwell needs to be connected to positive supply rail and pwell to negative supply rail (so that the parasitic diodes among them are reverse biased). Is this correct?

The RF and mmW devices are basically constrained to be 5/6T ones with all necessary guardrings included. If you will look carefully to property card of mmW fets, you will probably find that LLE effects are already included in these pcells (while in BB library the same fields are empty).
The purpose is to have a proper modeling of all effects important at mmW frequency range but also to match pre-layout and post-layout results. And yes, these diodes should be biased reversely.

- What would happen if I leave these well terminals floating? At schematic level, I can hardly observe any effect, but would there be issues in actual chip?

The most probably LVS and ERC rules will not allowed you to do that. However, at the output of such diode can be anything and it is hard to say what would happened. One would say, it would increase leakage, provides some strange high-frequency behavior, but I can only say that nothing good would happened.

 

[dick_freebird]

Depending on what the "I" is in SOI, you may
have different (or no) options.

Much "SOI" is really "SOIOS" (silicon on insulator
on silicon). Here, you could cut a deep trench
and plate it for a through-silicon via (TSV) and
get as much "grab" of the substrate, connected
to whatever you like on the chip directly.

You could also invoke a backside grind and
metallization, and a conductive die attach to
ohmically attach the substrate to the "paddle"
or heat slug (plastic pkgs) or the cavity floor
(alumina hermetic) of the package. This would
put a bond wire inductance between the
"handle" and the frontside, or two, which you
might mitigate by multiples in parallel.

Now I have spent much time with silicon-
on-sapphire product development and
there, there is no "there" there - just insulator
all the way down, nothing to connect to. This
is the earliest and true SOI (not SOIOx).

 

[big_fudge98]

Thanks, Dominik for the very detailed answer. I understand a lot more now.

--- Updated Feb 22, 2021 ---

Depending on what the "I" is in SOI, you may
have different (or no) options.

Much "SOI" is really "SOIOS" (silicon on insulator
on silicon). Here, you could cut a deep trench
and plate it for a through-silicon via (TSV) and
get as much "grab" of the substrate, connected
to whatever you like on the chip directly.

Hi, this is quite interesting. And you are right, the process is actually SOIOS. I can reach the bottom substrate if I draw a particular layer. The BOX would simply be excluded at that region.

Now I have spent much time with silicon-
on-sapphire product development and
there, there is no "there" there - just insulator
all the way down, nothing to connect to. This
is the earliest and true SOI (not SOIOx).

Is this why Silicon on Saphire gives the best mm-wave performance? The process would not be economical I guess.