Stupid VHDL little issue

[motote]

Hello, I'm getting mad trying to know why the data<= "000000001" assigment doen't work.
data is shifted in the right way, but it never get reassigned.

I should be a very stupid issue.... but I really can't see it.

Thanks!

---

Code VHDL - [expand]
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library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
  use UNISIM.VComponents.all;
 
 entity shifter is
  port ( Clk      : in    std_logic;
         led      : out   std_logic_vector(7 downto 0)
        );
 end shifter ;
 
 architecture Behavioral of shifter is
    signal data     : std_logic_vector(8 downto 0) := "000000101";
    signal hc        : std_logic_vector(9 downto 0) := (others => '0');
 begin
 process (clk)
  begin
    if rising_edge(clk) then
      if (hc(2 downto 0) = "000") then 
       data<= "000000001";    --<--- The problem is here
      end if;
          led <= data(8 downto 1);
      data(8 downto 1) <= data(7 downto 0);
      data(0) <= '0';
      hc <= hc + 1;
    end if;
  end process;
end behavioral;

---

 

[TrickyDicky]

because you always override it with

data(8 downto 1) <= data(7 downto 0);
data(0) <= '0';

Signals are scheduled to be updated - they are not updated immediatly. Hence they take the last thing assigned to them.

You probable want:

if (hc(2 downto 0) = "000") then 
  data<= "000000001";    --<--- The problem is here
else
  data(8 downto 1) <= data(7 downto 0);
  data(0) <= '0';
end if;

 

[mrflibble]

ROFL!!! Yay, I feel so validated. Also, are you reading minds TrickyDicky?

I swear I was about to post almost verbatim what you just wrote. Then I thought ... nah, I don't know VHDL well enough. Maybe there's something about how signal updates are done that are subtly different from how it's done in verilog. But apparently in VHDL it's pretty much the same thing.

*goes off looking for where that webcam is hiding out*

 

[TrickyDicky]

OT: I guess thats something to do with the blocking/non-blocking I keep reading about with Verilog

 

[motote]

I can see the problem, but I can't see the alternative code you proposed, just removed the hc increment.. then when can I increment it?
...And yes, I'm a C programmer trying to learn how to use FPGAs

 

[slirenem]

I'd like to meddle in because I'm learning now VHDL and I read that what is in process is executed sequentially. I thought I can expect that 'if' in motote code will be first and even if there are other assignments, they are after so they will wait. Are in process other legerdemains which impair sequential behaviour?

 

[alexan_e]

I think you need to read the difference between variables and signals

VHDL Tutorial

Apart from the fact that the signal is going to be assigned the value that was last given to it inside the process note that each time you are inside the process the value of the signal whenever referenced will be the one that was assigned to it in the previously executed process.
Whenever you use the data signal no matter what assignments you do to it, it will still holds the value that you gave to it in the previous executed process, it still has the old value.
The new assignment will be only valid the next time you enter the process.

 

[TrickyDicky]

I can see the problem, but I can't see the alternative code you proposed, just removed the hc increment.. then when can I increment it?

The HC increment would remain where it is (outside the if). The problem was with the data assignment.
Just to confuse your programmers brain more, you can use variables in VHDL, which are assigned immediatly, but as a beginner, I would ignore them for now (as code order becomes a greater factor in logic generation with them).

I'd like to meddle in because I'm learning now VHDL and I read that what is in process is executed sequentially. I thought I can expect that 'if' in motote code will be first and even if there are other assignments, they are after so they will wait. Are in process other legerdemains which impair sequential behaviour?

Yes processes are sequenction, but nothing waits in VHDL untill you hit a wait statement or a Process suspends (waiting for another event on a signal in the sensitivity list). So the last assignment is always taken. This is why sensitivity lists are so important in VHDL for simulation, because without one and no wait statements, a process loops forever at 0 time.

 

[motote]

Ok, I see now!... I didn't see the "else"... now I understand what you mean.. and why debugging with iSim the value didn't change.
Thanks very much!!!

 

[slirenem]

Thank you both very much for such a great clarification.