ST's Hysteresis voltage relation with power and frequency.

[imrankhanPNU]

Hello.
I would like a better understanding regarding Schmitt-trigger. What I know is: the wider the hysteresis width is, the more it provides noise immunity.

But I am curious about the relationship between incoming signal frequency and the hysteresis width?
And also the relationship of power and hysteresis width?

Thanks.

 

[danadakk]

Ignoring effects due to leakage currents.....

More questions, is the Hysteresis symmetrical at input, as this affects Rdson
related effects, Rload calculation, in case there is DC coupled loads

The energy dissipated in a CMOS inverter, most basic CMOS logic element, is
independent of Hysteresis (assuming only C type loads). If load has a DC
component in it then duty cycle and Hysteresis matters. Note NMOS inverter
a different consideration due to Pdiss related to PMOS current when output
is logic "0".

CMOS Inverter - Power and Energy Consumption

An in-depth guide on all the power and energy related phenomena inside the CMOS inverter and their mathematical calculations.

technobyte.org

With respect to frequency. Look at 74FC04 versus 74HC14 datasheets. Tpds ~ equal.
Tpd only affected from Hysteresis only from changes at extremes of Hysteresis levels.

Also I suspect noise related power dissipation affected by Hysteresis......?


Regards, Dana.

 

[FvM]

Hysteresis is implemented by positive feedback in the input stage, generally one pair of transistors driving against another one. During the transition, additional supply current is drawn. In case of fast input signal rise times, the additional losses are probably neglicible compared to load and internal capacitance related dynamic losses.

Besides supply voltage and signal rise time, the losses depend on transistor parameters. Changing the hysteresis involves a recalculation of transistor sizes and will most likely affect supply current in linear range. It's an IC design question.

 

[imrankhanPNU]

Thanks, @FvM and @danadakk for your response.
To be more specific, I have added schematic and related results.
I am retrieving the 1Mhz original message signal from the receiving signal, for that I used ST. In order to have a minimum signal delay, I am limited to a very narrow hysteresis width [show] based on the receiving signal. -Widening hysteresis leads to high signal delay, which is not appreciable. Furthermore, due to narrow hysteresis, the design is vulnerable to noise.
-How can I overcome these limitations and what will be the relation of hysteresis with power consumption and frequency (if freq changes from 1Mhz)

Thanks.

 

[FvM]

Compared to industry standard ST gates like HC14, the performance looks very poor, don't know why. I'd start ST gate models published by major manucturers.