pejotr
Newbie level 1
In the following code, which is well known 2 process state machine, if i comment line "if rising_edge(CK) then", corresponding "end if" and remove CK from sensitivity listi of e0 process it produces some strange results, why ?
Code:
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.binary_converters_pack.all;
entity operation is
generic ( n : natural := 8);
port ( M,Q : in std_logic_vector(n-1 downto 0);
RDY,CK : in std_logic;
RES : out std_logic_vector(n-1 downto 0);
BSY : out std_logic);
end entity operation;
architecture operation_arch of operation is
type state_type is (S0, S1);
signal res0 : std_logic_vector(n-1 downto 0);
signal a0, q0, m0 : unsigned(n-1 downto 0);
signal current_state, next_state : state_type;
begin
e0: process(CK, current_state) is
begin
if rising_edge(CK) then
for i in 0 to 6 loop a0(i+1) <= a0(i); end loop;
a0(0) <= RDY;
case current_state is
when S0 =>
next_state <= S1;
BSY <= '1';
when S1 =>
next_state <= S0;
BSY <= '0';
end case;
end if;
end process e0;
clk0: process(CK) is
begin
if rising_edge(CK) then RES <= std_logic_vector(a0); current_state <= next_state; end if;
end process clk0;
end architecture operation_arch;