rameshrai
Full Member level 3
Hi,
The system ports are declared std_logic_vector, it's subsystem has its port signed and unsigned type. Yet there is mapping of the ports between the system and subsystem although they have different type declaration.
does it imply there is automatic conversion from std_logic_vector to unsigned/ signed type?
thanks
The system ports are declared std_logic_vector, it's subsystem has its port signed and unsigned type. Yet there is mapping of the ports between the system and subsystem although they have different type declaration.
does it imply there is automatic conversion from std_logic_vector to unsigned/ signed type?
thanks