Zhane
Member level 5
State Machines
I have the above code implemented on a virtex 4 fpga, with in1,in2 and in3 as dip switches. state1 is the default state for 'state'.
I wanted something like this....
eg. when i set any of the dip switch (in1,in2 or in3) to high and then low, it increments the count once... until the next time i switch it to high-and-low again.
when the count hits >=90, the led is lit.
however when i tested it out on the fpga, without any clock and just the 2nd process alone... the LED blinks when i set in1/in2/in3 to high and held it there.
it seems that the increment is done many times while the in1/in2/in3 is being held when it should have been done once.
can anyone help me spot the error?
Code:
signal output: std_logic_vector(3 downto 0);
signal LED : std_logic_vector;
signal count : integer:=0;
process(clk)
begin
if(clk'event = true and clk='1') then
state <= nextState;
end if;
end process;
process(state,rst,in1,in2,in3)
begin
LED <= '0';
case state is
when state 1 =>
output <= "0010";
if(in1 = '1') then
count <= count +10;
elsif (in2 ='1') then
count <= count +5;
elsif (in3 ='1') then
count <= count +20;
end if;
if(count >90) then
LED <='1';
count <= 0;
end if;
when state 2=>
output<= "0001";
end case;
end if;
I have the above code implemented on a virtex 4 fpga, with in1,in2 and in3 as dip switches. state1 is the default state for 'state'.
I wanted something like this....
eg. when i set any of the dip switch (in1,in2 or in3) to high and then low, it increments the count once... until the next time i switch it to high-and-low again.
when the count hits >=90, the led is lit.
however when i tested it out on the fpga, without any clock and just the 2nd process alone... the LED blinks when i set in1/in2/in3 to high and held it there.
it seems that the increment is done many times while the in1/in2/in3 is being held when it should have been done once.
can anyone help me spot the error?