Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Stability Analysis of DCDC switch regulator

Status
Not open for further replies.

jackyhsu

Newbie level 4
Joined
Feb 4, 2005
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
70
regulator stability analysis

Dear advanced:
Like title ,does any one have experience about it (Boost or Buck)?
1.How to face switch on/off condition( to form dc bias)?
2.I kown there are average model in Book by Prof Erickson of Colorado university.
for example (CCM):
.subckt CCM2 1 2 3 4 5
+ Ron=0 VD=0 RD=0
Er 1 1x volt='i(Et)*(Ron+(1-v(5))*RD/v(5))/v(5)'
Et 1x 2 volt='(1-v(5))*(v(3,4)+VD)/v(5)'
Gd 4 3 volt='(1-v(5))*i(Et)/v(5)'
.ends
does anyone use it to analysis stability of dcdc switch converter?
Thanks.
 

sure, i have used the averaged switch models from erickson - they are pretty good. the model is just a model of the power stage - ie the modulator and switch. you add your own error amp to get a real converter that you can model. it's nice because you can run ac simulations to watch the gain/phase changes with load, etc.
 

    jackyhsu

    Points: 2
    Helpful Answer Positive Rating
I would prefer to run the simulation using Periodic Steady State of simulator such as Cadence. The results would be independent of models and we can really see the effects of comparator is tripping correctly and parasitics involved.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top