[STA] set_clock_skew & set_clock_uncertainty -> when used? why two commands?

[ivlsi]

Hi All,

Do the 'set_clock_skew' and 'set_clock_uncertainty' commands come to represent the same things? If they are then why two different commands are needed?

Thank you!

 

[yx.yang]

Re: [STA] set_clock_skew & set_clock_uncertainty -> when used? why two commands?

For detail explain of the two commands, you can use "man set_clock_skew" and "man set_clock_uncertainty" under DC.
To my understanding, "set_clock_skew" is mainly used when RTL synthesis to estimate the clock skew after Place&Route. After P&R, I ususally remove this command as the clock delay is known at this stage.
And "set_clock_uncertainty" is used both in RTL synthesis and STA after Place&Route. This is used to model the uncertainty in the design, such as PLL jitter, process caused uncertainty, .... .

 

[ivlsi]

Re: [STA] set_clock_skew & set_clock_uncertainty -> when used? why two commands?

set_clock_skew is an obsolete command ...

 

[yx.yang]

Re: [STA] set_clock_skew & set_clock_uncertainty -> when used? why two commands?

set_clock_skew is an obsolete command ...

Hi, dmitryl:
If you have know the answer, why you ask question here? I'm really confused.

 

[ivlsi]

Re: [STA] set_clock_skew & set_clock_uncertainty -> when used? why two commands?

I've got an answer to my question from another source and just wanted to update my friends on this forum. so, release your confusion, be happy