SRAM layout

[unix_amr]

Hello everyone;

I am designing a layout for a 6T-SRAM using Virtuoso Layout Editor based on TSMC 65nm PDK. I have drawn an isolated NP layer for each NMOS, but the layout area of SRAM is too large. Would it be possible to draw one large NP layer for all NMOS transistors?

Any help would be appreciated.

 

[Mushfiq_1p5]

Yes all the NMOS can share a common NP layer.
Because NP layer just indicates their implant type, nothing else.

 

[dick_freebird]

If you are following generic ground rules and using all ortho devices you are way behind the curve. The SRAM leaf cell is the key to it all, every legal cheat and trick applied and then negotiate some exceptions where another bit of area can be clawed back.

Often see SRAM-specific rules and flag-layers to back up all that.

Merging devices, using stretched S/D and gate poly for a very local interconnect, subminimum devices, it's all on the table in the 4-way chest bumping between design, CAD, reliability and marketing.