bubu_not_taken
Newbie level 3
Hello!
I'm trying to implement a spread spectrum clock generator using a digitally controlled delay line in Verilog.
The basic idea is that I'm trying to modulate the period of my clock signal using some and_gates that each have a delay value assigned to them. The delay network just delays the signal, but it does not change the period of the clock signal.
Is this concept even possible(modifying the period of the clock, by passing it through some and_gates) using Verilog?
Thank you very much!
I'm trying to implement a spread spectrum clock generator using a digitally controlled delay line in Verilog.
The basic idea is that I'm trying to modulate the period of my clock signal using some and_gates that each have a delay value assigned to them. The delay network just delays the signal, but it does not change the period of the clock signal.
Is this concept even possible(modifying the period of the clock, by passing it through some and_gates) using Verilog?
Thank you very much!