Spike at switch tansition

[okiiatama]

Hi all,

For a single nmos switch, what causes the transient spike at the transition from switch off to switch on?
Is there any method to eliminate this spike to get a smooth transition?

Thanks!!

 

[raduga_in]

MOS devices have inherent pracitic capacitance .. any sudden change in
gate voltage is reflected at the source or drain end due to the fundamental
property of capacitor which resist any sudden change of voltage across it.

This is the reason you have spike as you turn on and turn off the device.
Btw, about the reduction try using a dummy swich in series with the device,
which is nothing but a source drain shorted MOS transistor which is half the
size of the original switch .. more info is avialble in the doc attached
plz go through it ..

Regards

Raduga

 

[bharathi_dasan]

you can probably compare with traditional switch which draws more current while switching it on called transient.. due to the inrush current which takes its own time to settle due to the parasitic(incase of mos devices)

 

[okiiatama]

MOS devices have inherent pracitic capacitance .. any sudden change in
gate voltage is reflected at the source or drain end due to the fundamental
property of capacitor which resist any sudden change of voltage across it.

This is the reason you have spike as you turn on and turn off the device.
Btw, about the reduction try using a dummy swich in series with the device,
which is nothing but a source drain shorted MOS transistor which is half the
size of the original switch .. more info is avialble in the doc attached
plz go through it ..

Regards

Raduga

Is the solution of dummy switch is used to cancel charge injection? So is that means the positive-going spike during the switch is on also caused by charge injection? Most of the materials i went through before mention about the charge injection problem when the switch is off, but no material is explaining the spike when the switch is turned on.
I am wondering are that 2 spike due to the same reason or how...

Could you please give me further explaination ? Thanks!!

Added after 5 hours 50 minutes:

What is the relationship between the transistor gate length and the transition spike problem? i found that the spike is getting smaller when the gate length is reduced.

 

[TiwstedNeurons]

Like what raduga_in mentioned, the Cgs/Cgd can introduce the clk feedthrough, that's why if you decrease the L, Cgs/Cgd decrease correspondingly. So dummy transistor can absorb part of the charge injection and down play the clk feedthrough if my understanding is correct.