hmsheng
Full Member level 4
Circuit designer provides spice netlist (CDL out with Cadence) to Layout engineer for LVS. The spice netlist is modified manually. So we can't assure the syntex is right.
So I want to know if there is some tool that can be used to check the netlist and tell us the syntex error in it.
So I want to know if there is some tool that can be used to check the netlist and tell us the syntex error in it.