jerryjog
Junior Member level 1
spectreverilog
Hi there,
I'm a new user to cadence IC6.1 and I have some trouble getting the spectreVerilog simulator running properly. I've been using IC5141 for a long time and I simply followed the same steps in IC5141 to setup the spectreVerilog simulator in IC6.1. Here is my setup:
1. create schematic
2. create config file, link to schematic, specify view list and stop view list
3. In the schematic window, select mixed-signal optioins-->verimix, make sure the partitions are correct, assign digital output voltages
4. In ADE window, select spectreVerilog simulator, specifiy model library, run simulation....
Simulation results are the blocks implemented using verilog code are not simulated properly (all outputs are zero), I think they are not simulated at all.
Can anyone give me any advice?
Thanks
Jerry
Hi there,
I'm a new user to cadence IC6.1 and I have some trouble getting the spectreVerilog simulator running properly. I've been using IC5141 for a long time and I simply followed the same steps in IC5141 to setup the spectreVerilog simulator in IC6.1. Here is my setup:
1. create schematic
2. create config file, link to schematic, specify view list and stop view list
3. In the schematic window, select mixed-signal optioins-->verimix, make sure the partitions are correct, assign digital output voltages
4. In ADE window, select spectreVerilog simulator, specifiy model library, run simulation....
Simulation results are the blocks implemented using verilog code are not simulated properly (all outputs are zero), I think they are not simulated at all.
Can anyone give me any advice?
Thanks
Jerry
