specifiation to synthesis

[sagar_echip]

pls. suggest any large,well illustrated, design example in verilog,
in networking domain for study purpose.
(from specifiation to synthesis)

thanks

 

[windflower]

www.opencores.org, there are many example.

 

[reddy]

You can check out some codes in,
www.deeps.org

thanks,
-reddy

 

[delay]

Download working designs from www.xilinx.com

 

[claint]

There are some good books on EDAboard

 

[AlexWan]

pls. suggest any large,well illustrated, design example in verilog,
in networking domain for study purpose.
(from specifiation to synthesis)

If you have interesting in some core such as RISC 51 IP, you can send requisition to DCD Inc.
h**p://www.dcd.com.pl

Good Luck