some questions in syntheisable verilog

[THUNDERRr]

Hi all,
i have some question,
1- always @ * is not syntheisable , why?
2- if i have
wire [7:0] temp [3:0];
wire [1:0] temp1;

assign temp1 = temp[3] [1:0]; is not suntheisable why?
and what is the work around?

 

[ic_qiand]

Hi, could u tell me what do u mean by "*"?

And, for “assign temp1 = temp[3] [1:0]; ” Did u mean “assign temp1 = {temp[3], temp[1:0]}; ” ?

temp1 : 2-bit_wide
{temp[3], temp[1:0]}: 3-bit_wide

 

[THUNDERRr]

Hi ic_qiand ;
1-temp[3] [1:0] means select only the first two bits from element number 3 not the whole 8 bits.

2-always(*) it is a feature in verilog 2001 insead of using sensitivity lit

 

[ic_qiand]

Hi THUNDERRr

I didn't know the "always(*) " before, what a shame!!!

So u mean DC cant synthesize this “assign temp1 = temp[1:0];”

I think this evaluation between two wires just means a wire connect to the other.
It is meaningless except u want to change wires' names.
But u really dont need to do so while doing a functional description about a module.
U can evaluate a REG with “temp[1:0]” directly in always blocks.

If DC cant synthesize this, I guess, that's because in this path there's no start_point no end_point even no STD cells at all.

 

[rberek]

always @ (*) is most certainly synthesizeable. I've used it countless times before.

The ability to assign a vector to a portion of a vector array is not handled by many (if any) synthesis tools. An alternative is to create a third variable temp2 which is equal to temp[3]. Then do assign temp1 = temp2[1:0].

r.b.

 

[FvM]

Is it expecting too much to ask for a complete Verilog module that shows the problem?

 

[lostinxlation]

assign temp1 = temp[3] [1:0]; is not suntheisable why?
and what is the work around?

is that legal in verilog 2001 ? Certainly not legal with pre-verilog2001 according to the verilog book I read before.

If you want to do what you are intended in that statement, you need to do,
wire [1:0] temp1;
wire [7:0] temp2;
assign temp2 = temp[3];
assign temp1 = temp2[1:0];