Ian.Y.Jin
Newbie level 6
single nmos lvs
Dear All,
I'm currently working on a single transistor layout. The transistor has four pins in the schematic (namely, gate, source, drain and bulk). In the layout, I define four pins accordingly, using 'pin' layer for both pins and labels. But after LVS, none of the pins are recognized, and I have four ** missing port ** errors. Anybody has encountered same problem? Thanks.
Best Regards,
Ian Jin
Dear All,
I'm currently working on a single transistor layout. The transistor has four pins in the schematic (namely, gate, source, drain and bulk). In the layout, I define four pins accordingly, using 'pin' layer for both pins and labels. But after LVS, none of the pins are recognized, and I have four ** missing port ** errors. Anybody has encountered same problem? Thanks.
Best Regards,
Ian Jin