Simulation hanging.... What can be the causes..?

[vinun_7]

My question is related to verification.
If u r running a simulation (module level or full chip) and u have already made sure that
- clk/reset and other connectivities are okay
- the chip has booted properly
But the simulation hangs.
- Ur simulation time is not proceeding only delta is proceeding.
What could have gone wrong? What can be the things we can look for debugging...?

 

[avimit]

One of the possible causes of simulation hang is a what is called signal deadlock. It happens where 2 processes are involved, and one signal say A_sig in a process say process_A is waiting for a change in a signal, say B_sig in the another process, say process_B, and B_sig is waiting for a change in A_sig.
If you are working in VHDL, then improperly used wait statements are the most frequent cause of a simualtion hang.
hope it helps,
Kr,
Avi

 

[vinun_7]

Thanks Avi...

 

[santhosh007]

it could be with zero delay gate oscillation
If its NCverilog run with this option +ncgateloopwarn +ncaccess+c...
when it hangs.. interupt the simulation(Ctrl+c) then
ncsim> drivers -active
this tells you active drivers.. you add #1 for that cell.