Simulate an interconnection in Cadence Virtuoso

[fabhertz]

Hi everyone,
I am design some custom memory cells in Cadence Virtuoso, from the schematic to the layout production. I would like to design some basic blocks (for example, a row of memory cells) and interconnecting them in a SPICE netlist through scripting.

The problem is that I cannot find a way to define an input and an output pin for the beginning and the end of the row: since these would be connected by a metal1 layer, Virtuoso does not allow me to do it, since I am placing a short circuit between two differently named pins. Of course, the same applies at schematic level.

Have you any suggestion to implement this kind of block? I have thought about placing a null resistance in the schematic between the two pins, but I do not know how to implement this in the layout; furthermore, it is not an elegant/proper solution.

Thank you in advance for your suggestions.

Regards.

 

[dick_freebird]

a presistor will netlist as a Spectre resistor from schematic
for simulation, but a short for LVS. You can make its R
property a variable and then can switch topologies by
setting the variable(s).

 

[fabhertz]

a presistor will netlist as a Spectre resistor from schematic
for simulation, but a short for LVS. You can make its R
property a variable and then can switch topologies by
setting the variable(s).

Thank you for your answer.
Hence, you are suggesting to place a resistor in the schematic which resistance is an ADE variable? And in the LVS I will not get the short circuit error? What do you mean with and then can switch topologies by setting the variable(s)?
To be clear, I would like to put one pin at the beginning of the metal line (input)and another one at the end of the metal line (output), without having Virtuoso telling me that I cannot use two different pins names for the line ends.

In fact, this is the error that I get.

Thank you again for you help.

 

[timof]

You can use the same pin/port names on one net.
You need to use a command in parasitic extraction tool not to short them (with small resistor) - then, instead of two ports with the same name like "VSS", you will have two ports e.g. "VSS" and VSS_2".

You can also use presistor, as dick_freebird suggested above, but be careful with the names - after shorting the presistor, LVS selects one net name from two available names, and the rules determining which name is selected are very tricky (and if you do not pay attention to this, you may get completely wrong netlist, producing wrong simulation results).

 

[fabhertz]

Thank you for your answer @timof ,

You can use the same pin/port names on one net.
You need to use a command in parasitic extraction tool not to short them (with small resistor) - then, instead of two ports with the same name like "VSS", you will have two ports e.g. "VSS" and VSS_2".

I cannot find the command while running PEX. Can you be more specific? Thank you in advance. I am using Virtuoso 6.1.8.

This is the most similar option that I have found in the PEX settings. However, I am not able to get a second pin in the extracted netlist corresponding to the label that I added in the layout. Could you be more specific about the procedure that you have suggested? Thank you in advance.

 

[timof]

Thank you for your answer @timof ,

I cannot find the command while running PEX. Can you be more specific? Thank you in advance. I am using Virtuoso 6.1.8.
View attachment 171600
This is the most similar option that I have found in the PEX settings. However, I am not able to get a second pin in the extracted netlist corresponding to the label that I added in the layout. Could you be more specific about the procedure that you have suggested? Thank you in advance.

Did you add the points/ports at the top hierarchy level?

The GUI you show for extraction seems to be a custom GUI, internal to your company.
You can check with the documentation of your parasitic extraction tool, which command to use, in order not to short the ports, and to keep them unique in the extracted netlist.