Simple verilog question

[navie]

the simulator simply doesn't compile or issue an error

 

[zea505]

This is independent to simulators. The timing model should be defined by in verilog. This question is simply about the concept of concurrency and sequential structure.

All statements inside a always or initial block are processed sequentially and you can only see the final result. That means a = 0.

 

[cheney]

0, becasue verilog definition

 

[mmz25]

Simulated with ncverilog...

always @(posedge clk)
begin
a<=0;
a<=1;
end

Time                    0   a = x clk = 0
Time                    5   a = 1 clk = 1

always @(posedge clk)
begin
a<=1;
a<=0;
end

Time                    0   a = x clk = 0
Time                    5   a = 0 clk = 1


always @(posedge clk)
begin
a<=0;
end

always @(posedge clk)
begin
a<=1;
end

Time                    0   a = x clk = 0
Time                    5   a = 1 clk = 1

always @(posedge clk)
begin
a<=1;
end

always @(posedge clk)
begin
a<=0;
end


Time                    0   a = x clk = 0
Time                    5   a = 0 clk = 1

The second case is dicussed in Janick's book "Writing testbenches with systemverilog" and the simulation results agree to what is discussed in there..

HTH..

 

[learnbydo]

I think it is in race condition
The result is uncertain
Phehaps dependent on simulator or the context of simulation

 

[NuttyAvatar]

@verilog_always is right about the second case. This will cause multiple driver issue. And of course its unsynthesizeable.