simple layout question

[eng_islam]

why are ntaps and ptaps used

it is first time for my to make a layout on virtuoso XL and i have a silly question:-
in every componant in the kit there is a bulk terminal how i can connect it ?
for example :i use RF MOS and kit documents tell me that it is routto ME1 but i cant find it!!!!!!
another way to the question is there any method to to know the names of the transistor terminals in the layout?

thanx
eng_islam

 

[eng_Semi]

the bulk terminal is either connected to gnd or to vdd. u can check ur layout cell, if the bulk terminal is connected to the substrate, so it should be connected to gnd. If it is connected to N-WELL, it should be connected to vdd.

 

[eng_islam]

the bulk terminal is either connected to gnd or to vdd. u can check ur layout cell, if the bulk terminal is connected to the substrate, so it should be connected to gnd. If it is connected to N-WELL, it should be connected to vdd.

ok thanx i know that but i m asking about where is the bulk terminal in the layout i did not see it only i seee a 3 terminal device

 

[viren_s]

click on ur cell and check out the property ..see there bulk is in left or rught side or bulk is there or not?
if bulk is not there take on right or left sid e
i think u are missing this
hope this will help u

 

[dgy99]

in the case of CMOS with p-substrate,

the bulk of NMOS is the substrate, it's always connected to gnd,

and the bulk of PMOS is nwell surrounding PMOS.

 

[eng_islam]

i put a M1_NWELL contact just beside the NWELL then i connect it with the vdd
is that right?
when i did that the uncomplete net disappear
thanx

 

[gaoyanli]

m1_nwell cont should be placed inside nwell.
for example if you work in p-sub tech,always place con-wn in nwell and con-sub in sub as many as posible, to make nwell and sub connect to vcc and gnd very good!

 

[k_90]

For a P type device.
NO pcell shall have a "bulk" terminal. The schematic is looking for a connection to vdd. This is done by simply connecting the nwell to vdd by using a guard ring.
The same goes for a n type device except you will use an substrate tie.
I have been doing layout for over 6yrs now and I would always advice using guard rings around devices.

 

[eng_islam]

For a P type device.
NO pcell shall have a "bulk" terminal. The schematic is looking for a connection to vdd. This is done by simply connecting the nwell to vdd by using a guard ring.
The same goes for a n type device except you will use an substrate tie.
I have been doing layout for over 6yrs now and I would always advice using guard rings around devices.

thanx for this valuable information but could u tell me how can i put a gurd rings? this is my first time in making layout

Added after 15 minutes:

m1_nwell cont should be placed inside nwell.
for example if you work in p-sub tech,always place con-wn in nwell and con-sub in sub as many as posible, to make nwell and sub connect to vcc and gnd very good!

very good information for me thanx
but i searched in the contact menue in VERTOUSO and i do not find any con-sub anly con-nwell and con-Ndiff and cont-Pdiff
sall i use cont-pdiff as a bulk tie

 

[aomeen]

AA
Hello islaam.

most probabely the substrate is P, so it need be connected to the lowest potential "Ground" to make the substrate reverse biased, While the for PMOS, it must be put i an Nwell so It's connected to Vdd, again to make reverse bias.

you simply need to connect all the Nwell contacts together, all the Ptub contacts together, all vdd and all ground, dont cross connect Nwell to vdd, it's connected later.

Concerning guard ring, it's just a bulk tie surrounding the cell, like the one around the RF resistor or RF transistor, it's connected - as usal- to proper net "Ptub or Nwell"

One last thing, Some components"Like Cap's" will show both Nwell and Psub on schematic but only Nwell is valid for connectivity. It's OK. Connect the available one only and ignore the other, most proababely it is connected internally.

 

[cmos_dude]

Hi Aomeen,
What you have suggested is very informative, but the information limits itself to only a twin tub process.
How will you decide the subtrate contacts and the potentials of the respective substrates in a Triple well process ???

Regards
Cmos Dude

 

[aomeen]

No problems Dude

For trible well, both P and N MOS has their own well, For PMOS it's built in an Nwell on the substrate, so no problems.

For NMOS, a deep Nwell is built, into which many Pwells "For many NMOS devices" are built, each having it's own Pwell-i.e it's own substrate contact.

 

[rajkumaru]

Hi,
For vss connection u can use Psel+active+metal1
for vdd connection u can use Nsel+active+metal1

 

[ukint]

Generally taps are used for representing the bulk connections which also helps in reverse biasing the layer

 

[mac_user]

most of ptaps are connected to VSS and there will be no bulk for this , you can only change the bulk if you will use deep nwell.

regarding n-taps, this can be conncted to other bulks. if it has different bulk it should be isolated to other nwell