Signal routing: minimal width and space

[michcfr]

Hello,
I have a tiny PCB to route with very constrained space. Signals to be routed are: ADC, PWM, SPI, UART, I2C.
What is suggested, for each of these signals, the:
-minimal track width?
-minimal space within the signal group?
-minimal space to other signal group?

Thank you,

Regards,
Michel

 

[FvM]

Depends on your PCB makers capabilities and electrical requirements. These days, any pool PCB production can achieve at least 6 mil/0.15 mm structure size, means 0.15 mm width and clearance is possible for signal traces. Use a wider default width (at least 0.3 mm, better 0.5 mm) for power traces.

Capacitive coupling on a tiny PCB is limited due short length of parallel running traces. So if your design doesn't involve high speed or sensitive analog signals, you don't necessarily need larger class-to-class clearance. I would however distribute available room to achieve additional clearance.

 

[michcfr]

Depends on your PCB makers capabilities and electrical requirements. These days, any pool PCB production can achieve at least 6 mil/0.15 mm structure size, means 0.15 mm width and clearance is possible for signal traces. Use a wider default width (at least 0.3 mm, better 0.5 mm) for power traces.

Capacitive coupling on a tiny PCB is limited due short length of parallel running traces. So if your design doesn't involve high speed or sensitive analog signals, you don't necessarily need larger class-to-class clearance. I would however distribute available room to achieve additional clearance.

Thank you FvM for your response.

I agree, standard PCB makers can now even go down to 3.5mil for trace width and spacing.

10cm can be considered as a short length for parallel running traces? My PCB is narrow: 10cm length as a band of parallel running traces x 1cm width.
I also want to get benefit of the maximum speed of SPI, UART, I2C.

What do you think about these values: 4-5mil for track width, 5mil for space within the signal group, 15mil for space to other signal group?


thank you

 

[FvM]

The recommended clearance for cross talk isolation also depends on the stackup.
Depending on your PCB tool, there are options to implement cross talk clearance rules. Specctra router has e.g. parallel length dependant rules.

 

[michcfr]

Thank you for your response.

For information, I discovered the 3W rule to avoid crosstalk between parallel traces routed on the same layer: keep a minimum spacing between traces centers of 3xW (W: widt and space of the trace). 3W rule reduces the crosstalk by 70% (10W rule reduces the crosstalk by 98%).

Another rule: insert a guarding GND trace of W width between two traces

 

[KlausST]

Hi,

I personally never heard about 3W rule.

To me it makes not much sense, because:
* the trace width neither has something to do with inductive nor capacitve coupling.
* capacitive coupling depends on dV/dt of the signal, trace length and distance
* inductive coupling on dI/dt, trace length and distance.
* GND plane also will have influence,
* ...and medium, and signal impedance....

But you may use it. It won´t hurt.

Klaus

 

[michcfr]

thank you KlausST but it does not help me.