Signal Intergrity Related issues

[venkat_kvr]

hyperlynx

hii all can we discuss signal integrity related stuff theory,tools etc here

Added after 1 minutes:

I am Mentor graphics hyperlynx user if u have any doubts regarding hyperlynx ask me

 

[prasad5551]

series switch groups

I am new to hyperlynx.pls can you give the guidelines for signal integrity and EMC/EMI,cross talk. tips and tricks and general guidelines while designing

 

[venkat_kvr]

series switch hyperlynx

Go through the Hyperlynx demonstration tutorial, it will explain all the basic concepts

 

[s3034585]

hyperlynx emc tutorial

Hi Venkat_kvr

I am trying to use Hyperlynx 7.2 software for my project. After going throught the tutorials, i tried to simulate my project. But i am unable to the same results as we got in the tutorials. My board has 5282 processor, cpld, fpga, flash and a level translator.
When i run the entire simulation with all these components the waveform looks shocking.. the output of driver which is 5282 shows huge ammount of overshoot. So we ran the simulation again with just 5282 and level translator(end device) but still the waveform dosnt improve. Total trace lenght is 6.5inch..



i am unable to understand whether there is something wrong in the simulation setup or not.

it would be nice if you can give throw more light on this....

Thanks
tama

 

[venkat_kvr]

guidelines to use hyperlynx

Hi Tama

You will get the same results as tutorial whn u use same IBIS models and routing topology.

U have simulated at 133MHz is ur driver capable of driving at tht frequncy?chk it in the datashhet

also try different routing topology

 

[s3034585]

hyperlynx v7.7

Hi Venkat_kvr
thanks for ur reply... I am using the same ibis models which are avaliable in the lib and other from the suppliers. the driver is working at 50Mhz.. . is this correct way to see the complete cycle.... u mentioned about diff routing style. as off now i am just simulation 2 components at a time that too only one add line from the enitre add bus... as i had previously mentioned the compoents on the board which share add and data bus.... what do you recomend for such kind of routing....

thanks
tama

 

[venkat_kvr]

signal intergrity

Hi Tama,

Increase the Time scale in the oscilloscope to see the full cycle . Try with Daisy chain topology with minimum stub lengths.

 

[dollymitra]

ibis mosfet series bus switch example

hi everyone

I am a pcb layout designer since last ten years.
I want to learn post layout simulation . I have orcad 10.5 & dxp2004.
I don't know how to start ?
Pl.help me

 

[s3034585]

switch bus serie mosfet hyperlynx

Hi Venkat

Thanks for ur response... can you pls share some info on what steps you generally follow while designing a pcb. what i want to know is at what stages do you do simulations... i know we can do it before layout and post layout.

in my have just routed the add and data bus... it is but obvious that the lenght is not going to be same. so is it a gd idea to do simulations at this stage or after you match the lenghts... secondly to what extend one should say that the waveforms are ok. what i mean is that the driver will always have some sort of oscialltions over the edges as compared to the receviers. espically when the entire trace lenght is in the range of 6-7inch at 50Mhz.

what kind of board frequencys are your boards.

Thanks
tama

 

[venkat_kvr]

hyperlynx v7.7 license

Hii Tama

1."is it a gd idea to do simulations at this stage or after you match the lenghts"
It is good to perfomr the analysis first and then goto length matching

2."what extend one should say that the waveforms are ok"
as long as it meets the timing(setup/Hold) requirements also the overshoot/undershoot canot exceed the max spec given in the datasheet.If it a clock signal the edges should be clean.

 

[s3034585]

series mosfet ibis mentor

Hi Venkat

i am trying to simulate nets with 5.5inch lengh connecting to 4 devices with a series resistor of 33R( i know this needs to be adjusted) but the results what i get are pretty much like a capacitor charging and discharging... i went through the tutorial again and saw that they simulate a net of 7.5 inchs but still the waveform is better. i dont understand whats going wrong. is there a problem with the ibis models or some software settings... i have attached the waveform and the net also... can you pls help me solve the problem.





thanks
tama

 

[venkat_kvr]

hyperlynx switch model

Its look like the signal have more loading can u reduce the trace length and series resistance value and simulate once?

 

[s3034585]

intergrity related issues in service department

Hi Venkat

I tried to simulate again with small value resistor 15R... but still the waveform didnt improve much. i cant reduce the lenght any further as it is the shortest to connect all the devices.... considering other data lines...

then i tried to simulate lower half of the data bus which connects 3 devices..and the lenght is 2.6 inch... but for this also the waveform is not better... bit improved as compared to the upper half databus... I have attached the waveform.. series resistor is 22ohms..



i am unable to understand wht is gng wrong... how do i improve this waveform..

thanks
tama

 

[venkat_kvr]

how to simulate bus switch in hyperlynx

Hi Tama

Can u upload the routing topology of the net?

 

[pramodm]

Hi

I am new to board design. i would like to know what are the things we can do with hyperlynx in board design ??

thanx

 

[venkat_kvr]

Hi

I am new to board design. i would like to know what are the things we can do with hyperlynx in board design ??

thanx

You Can Perfrom SI and EMI Analysis using Hyperlynx

 

[s3034585]

Hi Venkat

i have attached the net routing.. it seems the processor cant handle load of 4 devices. hence we tried to add a buffer and the results do improve but still the termination ?? is there... so we tried to simulate with pull up at both the ends (because its a multi drop bus)of the bus to 1.25v. similar to DDR2. The wavefrom is much better than without a buffer. but Vp-p is not more than 2-2.5V.. can this be a issue..




thanks
tama

 

[venkat_kvr]

Hi Venkat

i have attached the net routing.. it seems the processor cant handle load of 4 devices. hence we tried to add a buffer and the results do improve but still the termination ?? is there... so we tried to simulate with pull up at both the ends (because its a multi drop bus)of the bus to 1.25v. similar to DDR2. The wavefrom is much better than without a buffer. but Vp-p is not more than 2-2.5V.. can this be a issue..




thanks
tama

Hi Tama

Is ur devices are operating at 3.3V? chkout noise margin of the signals. Have u tried series termiantion.

 

[KP]

Hi
I wonder how much does it cost to purchase license of hyperlynx software
for V7.2...?
I m newbie to this ...

Added after 26 seconds:

Hi
I wonder how much does it cost to purchase license of hyperlynx software
for V7.2...?
I m newbie to this ...

 

[pankaj]

Dear Venkat,

Can you tell me how to simulate a series switch model on Hyperlynx 7.7.
Specifically I want to simulate bus switch from TI SN74CB3T16211. The ibis model from TI (any other vendor also like Fairchild) have defined all the pins as input and not as output.
In cadence they have a method to convert this model into an input-output model but the method for Hyperlynx is not known to me. My support for Mentor Graphics has expired and hence I am not getting any reply from them.


With regards
Pankaj