Signal do not get value

[sinnadyr]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity edge_sobel is
	 generic ( PWIDTH   : integer := 8);
    port ( 
				pclk_i	: in std_logic;
				fsync_i	: in std_logic;
				rsync_i	: in std_logic;
				p1 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				p2 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				p3 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				p4 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				p5 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				p6 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				p7 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				p8 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				p9 		: in STD_LOGIC_VECTOR(pwidth-1 downto 0) := "11111111";
				
				fsync_o		: out std_logic;
				rsync_o		: out std_logic;
				pdata_o		: out std_logic_vector(pwidth-1 downto 0)
			  );
			  
end entity edge_sobel;

architecture Behavioral of edge_sobel is

signal Gx : STD_LOGIC_VECTOR(pwidth-1 downto 0);
signal Gy : STD_LOGIC_VECTOR(pwidth-1 downto 0);
signal G : STD_LOGIC_VECTOR(pwidth-1 downto 0);
signal Gx_x : STD_LOGIC_VECTOR(pwidth-1 downto 0);
signal Gy_y : STD_LOGIC_VECTOR(pwidth-1 downto 0);

begin
	dummy_edge_sobel: process (pclk_i)
	begin  
		if (pclk_i'event and pclk_i = '1') then 

	Gx <=(p3-p1)+((p6(6 downto 0) & '0')-(p4(6 downto 0) & '0')) + (p9-p7); -- p6(6 downto 0) & '0')as a shift of one bit
	Gy <=(p7-p1)+((p8(6 downto 0) & '0')-(p2(6 downto 0) & '0')) + (p9-p3); -- p8(6 downto 0) & '0') as a shift of one bit

	if Gx(7)='1' then  
		Gx_x<= not Gx + 1;
	else
		Gx_x<= Gx;				
	end if;

	if Gy(7)='1' then
		Gy_y<= not Gy + 1;
	else
		Gy_y<= Gy;
	end if;
	
	G<=Gx_x+Gy_y;
	 -- Doing Threshold 127

end if;
	end process dummy_edge_sobel;
	
end Behavioral;

Hi,

I am trying to simulate a sobel filter in ModelSim using ISE from Xilinx. The problem is that Gx and Gy is getting good values, bot I can not summarize them in to G.
ModelSim give me a couple of these:

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
# Time: 1 us Iteration: 0 Instance: /edge_sobel

The console in ISE says as a warning

WARNING:Xst:646 - Signal <G> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

The calculations of Gx and Gy was first expected to be 9 bit, so G should be a vector of 8 downto 0. Caused the same problem so now we tried this. I am having a little trouble understanding my teachers sollution, especially the Gx_x <= not Gx +1, especially when I have no experience with VHDL from before.

Any help on this matther is really appreciated!
Thank you

 

[vahidkh6222]

I think the problem is you haven't assigned any value to the output ports!
So the synthesiser tool sees that non of the calculations of internal signal is really necessary, so it deletes them.

For preliminary simulations, just declare some temporary ports and assign internal signals to them.
For instance, G can be an output port instead of a signal.