Should there always be a rest??

[hallovipin]

What is the purpose of reset as ISE itself initialize all registers to 0 at the start of execution.

comment?/

 

[Umair_ali]

for simulation purposes, its mendatory to restart few regs for e.g. if you r doing somthing like that

cout = count + 1

you must have to reset your "count" register

 

[TrickyDicky]

what about when you want to powerup or reset to '1'?
initial states need to be reset.
counters.

Then there is the issue of simulation, where everything defaults to 'U' in VHDL.

 

[FvM]

Most programmable logic devices (CPLD or FPGA) have a power-on reset as a hardware feature. There may be also an option to connect a dedicated reset input to the existiing reset logic.

Complex design usually need reset functionality in the user logic, in most cases, an external reset should be synchronized to the clock to achieve reliable behaviour.

Possible discrepancy between synthesis and functional simulation is a special issue. The 'U' problem with uninitialized signals, although mostly annoying, should be understand as a feature to warn the designer about missing reset for particular signals. If you're sure you want just rely on the power-on default, simply add an initial state to the signal definition. It will be correctly understood by both, design compiler and simulator.

 

[hallovipin]

What is this 'U' problem. I am using Verilog and the simulation after synthesis works fine for me.
@ FVM
What I learnt that 'initial' block is not considered at the time of synthesis. So how to initialize signals without reset?

By default every register and variable is set to 0 on the power up.

 

[FvM]

What is this 'U' problem.

ModelSim is assuming 'u' for all uninitialized signals.

What I learnt that 'initial' block is not considered at the time of synthesis.

It depends on your synthesis tool. Altera Q.uartus is implementing Verilog initial blocks respectively initialized VHDL signals by hardware power-on reset condition. But I see, that they are ignored e.g. by the Synopsys design compiler. I don't know about other tools.

 

[hallovipin]

ISE doent consider them.

 

[lucbra]

It is always a good practice to add a reset condition to a process.

POR is just what it says it is: reset at power on, thus not a controlled way of resetting your signals to a certain condition.

Even if ISE adds the reset itself, you never know if you are going to use ISE tomorrow again, and then you have a problem.

 

[mansi0905]

yes there should always be a reset . it prevents the signals from getting undefined values or garbage values especially when you do hardware implementation