setup hold time violation in ISE

[Tomby]

xilinx hold violation

Hello,

I have synthesized, and run the translate, map, place and route for the virtexe fpga in ISE5.1i but when I try to simulate the netlist that ISE5.1i generates along with the sdf file I get these errors.

# Time: 1733 ps Iteration: 0 Instance: /uart_tb/uart_top_postsim/u_550_linectlreg_3
# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(54): $setup( negedge CE &&& (ce_clk_enable == 1):1265 ps, posedge CLK:1733 ps, 686 ps );

It says an error with the setup time being smaller than what it should be. Shouldn't Xilinx take care of this automatically when it is mapping and routing the actual fpga to ensure all the setup and hold times of all the blocks are taken into account?

Tomby

 

[shengkaiyi]

xilinx hold time violation

Your timing violation happens at the very beginning intial time. If the violation does not affect your simulation result, you can ignore it. If it really affect the result, you should use the constraints file to limit the synthesis process and the p&R process.

 

[Tomby]

setup and hold time+xilinx

Thanks but modelsim won't even start to simulate due to this error. I will try to check the constraints file to see how I might be able to fix it.

 

[massive]

what is hold time violation

Ones I've had the same problem!
What is the decision?

May be You can search an answer record in the Xilinx Web site..

 

[skynet]

hold time violation xilinx

How about using Xilinx STA timing analyzer to see what is your problems before go to Post Place & Route Simulation??

 

[Tomby]

ise ignore timing constraints

I tried searching the Xilinx site but havent found any useful info. I did find an answer for a similar problem in 4.1i. I am running Xilinx STA and have yet to find any problems.

The sdf file that is generated by ise 5.1 seems to be the problem and although I did define my constraints file properly, it still has the setup hold violation problem in the sdf file.

 

[skynet]

ise setup/hold

Let go step by step. I did not agree that the problem come from sdf file. How about you try to slower down your clock frequency inside ur test bench??

 

[zhangyong]

setup/hold time

YOu try sim without using sdf file, comment the initiate sdf in sim model file.

This will only sim the model function without timing test

 

[silver_kiss]

xilinx hold time violations

just go through this xilinx application note..basics of setup,hold

 

[Tomby]

modelsim hold violation

I have tried simulating it without any timing constraints(no sdf) and it passes perfectly. I have also tried slowing down the only clock in the system and still gives me the same problem.

The same problem in ISE4.1i was solved with a service pack upgrade, I was thinking maybe this is the same issue in 5.1i?

Thanks.

Tomby