Tomby
Junior Member level 2
xilinx hold violation
Hello,
I have synthesized, and run the translate, map, place and route for the virtexe fpga in ISE5.1i but when I try to simulate the netlist that ISE5.1i generates along with the sdf file I get these errors.
# Time: 1733 ps Iteration: 0 Instance: /uart_tb/uart_top_postsim/u_550_linectlreg_3
# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(54): $setup( negedge CE &&& (ce_clk_enable == 1):1265 ps, posedge CLK:1733 ps, 686 ps );
It says an error with the setup time being smaller than what it should be. Shouldn't Xilinx take care of this automatically when it is mapping and routing the actual fpga to ensure all the setup and hold times of all the blocks are taken into account?
Tomby
Hello,
I have synthesized, and run the translate, map, place and route for the virtexe fpga in ISE5.1i but when I try to simulate the netlist that ISE5.1i generates along with the sdf file I get these errors.
# Time: 1733 ps Iteration: 0 Instance: /uart_tb/uart_top_postsim/u_550_linectlreg_3
# ** Error: C:/Xilinx/verilog/src/simprims/X_FF.v(54): $setup( negedge CE &&& (ce_clk_enable == 1):1265 ps, posedge CLK:1733 ps, 686 ps );
It says an error with the setup time being smaller than what it should be. Shouldn't Xilinx take care of this automatically when it is mapping and routing the actual fpga to ensure all the setup and hold times of all the blocks are taken into account?
Tomby